Fast-locking phase-error compensation technique in PLL

Bumsoo Lee; Chan Hui Jung; Se Chun Park; Soo Won Kim

doi:10.1109/ICSICT.2012.6467809

Fast-locking phase-error compensation technique in PLL

Bumsoo Lee, Chan Hui Jung, Se Chun Park, Soo Won Kim

* Honorary professors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This work represents a phase-locked loop (PLL) which has fast locking time. The proposed phase-error compensation technique is conducted by delay cells and switches used for compensating phase-error during frequency hop. And a conventional digital discriminator aided phase detector (DAPD) is used for lock detector. The DAPD continuously detects the phase difference and enlarges the bandwidth of PLL by changing the charge pump currents, loop filter. During the frequency tracking with wide bandwidth, phase-error compensation block adjust the delay of output of programmable divider by the polarity of phase-error The proposed technique is incorporated in the design of a 1.55-GHz PLL. Simulated in the Dongbu 0.11-μm CMOS technology, the whole PLL dissipates 0.97mW from 1.2-V supply. The measured settling time, 1.5-μs, is improved compared to bandwidth switching technique.

Original language	English
Title of host publication	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs	https://doi.org/10.1109/ICSICT.2012.6467809
Publication status	Published - 2012
Event	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China Duration: 2012 Oct 29 → 2012 Nov 1

Publication series

Name	ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other	2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
Country/Territory	China
City	Xi'an
Period	12/10/29 → 12/11/1

ASJC Scopus subject areas

Human-Computer Interaction
Electrical and Electronic Engineering

Access to Document

10.1109/ICSICT.2012.6467809

Cite this

Lee, B., Jung, C. H., Park, S. C., & Kim, S. W. (2012). Fast-locking phase-error compensation technique in PLL. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings [6467809] (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2012.6467809

Fast-locking phase-error compensation technique in PLL. / Lee, Bumsoo; Jung, Chan Hui; Park, Se Chun et al.
ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467809 (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, B, Jung, CH, Park, SC & Kim, SW 2012, Fast-locking phase-error compensation technique in PLL. in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 6467809, ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012, Xi'an, China, 12/10/29. https://doi.org/10.1109/ICSICT.2012.6467809

Lee B, Jung CH, Park SC, Kim SW. Fast-locking phase-error compensation technique in PLL. In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2012. 6467809. (ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2012.6467809

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Fast-locking phase-error compensation technique in PLL

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