Fast VLSI motion estimator based on bit plane matching

Y. K. Ko; H. G. Kim; H. C. Oh; S. J. Ko

doi:10.1049/el:20001342

Fast VLSI motion estimator based on bit plane matching

Y. K. Ko, H. G. Kim, H. C. Oh, S. J. Ko

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.

Original language	English
Pages (from-to)	1923-1924
Number of pages	2
Journal	Electronics Letters
Volume	36
Issue number	23
DOIs	https://doi.org/10.1049/el:20001342
Publication status	Published - 2000 Nov 9

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1049/el:20001342

Cite this

@article{d85fae4074084e20b22e093947628edc,

title = "Fast VLSI motion estimator based on bit plane matching",

abstract = "A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.",

author = "Ko, {Y. K.} and Kim, {H. G.} and Oh, {H. C.} and Ko, {S. J.}",

year = "2000",

month = nov,

day = "9",

doi = "10.1049/el:20001342",

language = "English",

volume = "36",

pages = "1923--1924",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "23",

}

TY - JOUR

T1 - Fast VLSI motion estimator based on bit plane matching

AU - Ko, Y. K.

AU - Kim, H. G.

AU - Oh, H. C.

AU - Ko, S. J.

PY - 2000/11/9

Y1 - 2000/11/9

N2 - A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.

AB - A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.

UR - http://www.scopus.com/inward/record.url?scp=0034322789&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034322789&partnerID=8YFLogxK

U2 - 10.1049/el:20001342

DO - 10.1049/el:20001342

M3 - Article

AN - SCOPUS:0034322789

SN - 0013-5194

VL - 36

SP - 1923

EP - 1924

JO - Electronics Letters

JF - Electronics Letters

IS - 23

ER -

Fast VLSI motion estimator based on bit plane matching

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this