A fast VLSI motion estimator based on bit plane matching is proposed. The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilize lower-cost fabrication technology.
|Number of pages||2|
|Publication status||Published - 2000 Nov 9|
ASJC Scopus subject areas
- Electrical and Electronic Engineering