Fault tolerance technique offlining faulty blocks by heap memory management

Jaeyung Jun, Yoonah Paik, Gyeong Il Min, Seon Wook Kim, Youngsun Han

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


As dynamic random access memory (DRAM) cells continue to be scaled down for higher density and capacity, they have more faults. Thus, DRAM reliability becomes a major concern in computer systems. Previous studies have proposed many techniques preserving the reliability in various system components, such as DRAM internal, memory controller, caches, and operating systems. By reviewing the techniques, we identified the following two considerations: First, it is possible to recover faults with reasonable overhead at high fault rate only if the recovery unit is fine-grained. Second, since hardware modification requires additional cost in the employment of a technique, a pure software-based recovery technique is preferable. However, in the existing software-based recovery technique, the recovery unit is too coarse-grained to tolerate the high fault rate. In this article, we propose a pure software-based recovery technique with fine-granularity. Our key idea is based on heap segments being managed by the system library with variable-sized chunks to handle dynamic allocation in user applications. In our technique, faulty blocks in pages are offlined by marking them as allocated chunks. Thus, not only fault-free pages but also the remaining clean blocks in faulty pages are allowed to be usable space. Our technique is implemented by modifying the operating system and the system library. Since hardware assistance is unnecessary in the implementation, we evaluated our method on a real machine. Our evaluation results show that our technique has negligible performance overhead at high bit error rate (BER) 5.12e-5, which a hardware-based recovery technique could not tolerate without unacceptable area overhead. Also, at the same BER, our method provides 5.22× usable space, compared with page-offline, which is the state-of-the-art pure software-based technique.

Original languageEnglish
Article number47
JournalACM Transactions on Design Automation of Electronic Systems
Issue number4
Publication statusPublished - 2019 Jun

Bibliographical note

Funding Information:
This work was supported by the IT R&D program of MOTIE/KEIT [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC]. Authors’ addresses: J. Jun, Y. Paik, G. Min, and S. W. Kim (corresponding author), 415 New Engineering Hall, Korea University, Seoul, Korea, 02841; emails: {cool92-3, yoonpaik, gyeong9m, seon}@korea.ac.kr; Y. Han, 202 the 2nd Engineering Building, Kyungil University, Gyeongsan, Korea, 38428; email: youngsun@kiu.ac.kr. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2019 Association for Computing Machinery. 1084-4309/2019/05-ART47 $15.00 https://doi.org/10.1145/3329079

Publisher Copyright:
© 2019 Association for Computing Machinery.


  • DRAM fault recovery

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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