We present a capacitor-less 1T-DRAM cell on SiO$-2$ /Si substrates using a silicon nanowire (SiNW) as the channel material. The SiNWs are fabricated by a top-down route that is fully compatible with the current Si-based CMOS technology. Based on the observation of the floating body effect of a partially depleted (PD) silicon nanowire transistor (SNWT), its 1T-DRAM functionality and reliability characteristics are investigated. By virtue of the top-down route providing a printable form of the inverted triangular SiNWs, the PD SNWT 1T-DRAM cell can be applied on insulating plastic substrates for potential applications of flexible electronics.
Bibliographical noteFunding Information:
Manuscript received August 30, 2011; accepted November 2, 2011. Date of publication November 16, 2011; date of current version March 9, 2012. This work was supported in part by the Future-Based Technology Development Program (Nano Fields) through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science, and Technology under Grant 2010-0019197, the World Class University under Grant R32-2008-000-10082-0, the IT R&D program of MKE/KEIT under Grant 10030559 [development of next generation high performance organic/nano materials and printing process technology], the Seoul R&BD Program under Grant PA090914, and the KSSRC program [development of printable integrated circuits based on inorganic semiconductor nanowires]. The review of this paper was arranged by Associate Editor R. Lake.
- floating body effect
- partially depleted (PD)
- silicon nanowire transistor (SNWT)
ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering