FPGA reverse engineering in Vivado design suite based on X-ray project

Hoyoung Yu; Hyung Min Lee; Youngjoo Shin; Youngmin Kim

doi:10.1109/ISOCC47750.2019.9078504

FPGA reverse engineering in Vivado design suite based on X-ray project

Hoyoung Yu
, Hyung Min Lee
, Youngjoo Shin
, Youngmin Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.

Original language	English
Title of host publication	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	239-240
Number of pages	2
ISBN (Electronic)	9781728124780
DOIs	https://doi.org/10.1109/ISOCC47750.2019.9078504
Publication status	Published - 2019 Oct 1
Event	16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of Duration: 2019 Oct 6 → 2019 Oct 9

Publication series

Name	Proceedings - 2019 International SoC Design Conference, ISOCC 2019
Volume	2019-January

Conference

Conference	16th International System-on-Chip Design Conference, ISOCC 2019
Country/Territory	Korea, Republic of
City	Jeju
Period	19/10/6 → 19/10/9

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This research was supported by the Basic Science Research Program, through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (NRF-2017R1D1A1B03028065).

Publisher Copyright:
© 2019 IEEE.

Keywords

FPGA
Non-invasive attack
Reverse engineering

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC47750.2019.9078504

Cite this

Yu, H., Lee, H. M., Shin, Y., & Kim, Y. (2019). FPGA reverse engineering in Vivado design suite based on X-ray project. In Proceedings - 2019 International SoC Design Conference, ISOCC 2019 (pp. 239-240). Article 9078504 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC47750.2019.9078504

FPGA reverse engineering in Vivado design suite based on X-ray project. / Yu, Hoyoung; Lee, Hyung Min ; Shin, Youngjoo et al.
Proceedings - 2019 International SoC Design Conference, ISOCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 239-240 9078504 (Proceedings - 2019 International SoC Design Conference, ISOCC 2019; Vol. 2019-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yu, H, Lee, HM , Shin, Y & Kim, Y 2019, FPGA reverse engineering in Vivado design suite based on X-ray project. in Proceedings - 2019 International SoC Design Conference, ISOCC 2019., 9078504, Proceedings - 2019 International SoC Design Conference, ISOCC 2019, vol. 2019-January, Institute of Electrical and Electronics Engineers Inc., pp. 239-240, 16th International System-on-Chip Design Conference, ISOCC 2019, Jeju, Korea, Republic of, 19/10/6. https://doi.org/10.1109/ISOCC47750.2019.9078504

@inproceedings{f299e1b13b824f519818763334f086a9,

title = "FPGA reverse engineering in Vivado design suite based on X-ray project",

abstract = "As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies. ",

keywords = "FPGA, Non-invasive attack, Reverse engineering",

author = "Hoyoung Yu and Lee, \{Hyung Min\} and Youngjoo Shin and Youngmin Kim",

note = "Funding Information: ACKNOWLEDGMENT This research was supported by the Basic Science Research Program, through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (NRF-2017R1D1A1B03028065). Publisher Copyright: {\textcopyright} 2019 IEEE.; 16th International System-on-Chip Design Conference, ISOCC 2019 ; Conference date: 06-10-2019 Through 09-10-2019",

year = "2019",

month = oct,

day = "1",

doi = "10.1109/ISOCC47750.2019.9078504",

language = "English",

series = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "239--240",

booktitle = "Proceedings - 2019 International SoC Design Conference, ISOCC 2019",

}

TY - GEN

T1 - FPGA reverse engineering in Vivado design suite based on X-ray project

AU - Yu, Hoyoung

AU - Lee, Hyung Min

AU - Shin, Youngjoo

AU - Kim, Youngmin

N1 - Funding Information: ACKNOWLEDGMENT This research was supported by the Basic Science Research Program, through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (NRF-2017R1D1A1B03028065). Publisher Copyright: © 2019 IEEE.

PY - 2019/10/1

Y1 - 2019/10/1

N2 - As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.

AB - As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project [1] is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies.

KW - FPGA

KW - Non-invasive attack

KW - Reverse engineering

UR - https://www.scopus.com/pages/publications/85087824365

U2 - 10.1109/ISOCC47750.2019.9078504

DO - 10.1109/ISOCC47750.2019.9078504

M3 - Conference contribution

AN - SCOPUS:85087824365

T3 - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

SP - 239

EP - 240

BT - Proceedings - 2019 International SoC Design Conference, ISOCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th International System-on-Chip Design Conference, ISOCC 2019

Y2 - 6 October 2019 through 9 October 2019

ER -

FPGA reverse engineering in Vivado design suite based on X-ray project

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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