Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme

Woong Choi; Hoonki Kim; Changnam Park; Taejoong Song; Jongsun Park

doi:10.1109/VLSIC.2018.8502311

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme

Woong Choi, Hoonki Kim, Changnam Park, Taejoong Song, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	17-18
Number of pages	2
ISBN (Electronic)	9781538667002
DOIs	https://doi.org/10.1109/VLSIC.2018.8502311
Publication status	Published - 2018 Oct 22
Event	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 2018 Jun 18 → 2018 Jun 22

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2018-June

Other

Other	32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Country/Territory	United States
City	Honolulu
Period	18/6/18 → 18/6/22

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/VLSIC.2018.8502311

Cite this

Choi, W., Kim, H., Park, C., Song, T., & Park, J. (2018). Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 (pp. 17-18). Article 8502311 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2018.8502311

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. / Choi, Woong; Kim, Hoonki; Park, Changnam et al.
2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 17-18 8502311 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, W, Kim, H, Park, C, Song, T & Park, J 2018, Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. in 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018., 8502311, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 17-18, 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018, Honolulu, United States, 18/6/18. https://doi.org/10.1109/VLSIC.2018.8502311

Choi W, Kim H, Park C, Song T, Park J. Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. In 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 17-18. 8502311. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2018.8502311

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AB - In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.

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Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme

Abstract

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ASJC Scopus subject areas

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