TY - GEN
T1 - Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme
AU - Choi, Woong
AU - Kim, Hoonki
AU - Park, Changnam
AU - Song, Taejoong
AU - Park, Jongsun
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/22
Y1 - 2018/10/22
N2 - In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.
AB - In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.
UR - http://www.scopus.com/inward/record.url?scp=85056839328&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2018.8502311
DO - 10.1109/VLSIC.2018.8502311
M3 - Conference contribution
AN - SCOPUS:85056839328
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 17
EP - 18
BT - 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Y2 - 18 June 2018 through 22 June 2018
ER -