Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme

Woong Choi, Hoonki Kim, Changnam Park, Taejoong Song, Jongsun Park

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    16 Citations (Scopus)

    Abstract

    In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.

    Original languageEnglish
    Title of host publication2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages17-18
    Number of pages2
    ISBN (Electronic)9781538667002
    DOIs
    Publication statusPublished - 2018 Oct 22
    Event32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States
    Duration: 2018 Jun 182018 Jun 22

    Publication series

    NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
    Volume2018-June

    Other

    Other32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
    Country/TerritoryUnited States
    CityHonolulu
    Period18/6/1818/6/22

    Bibliographical note

    Publisher Copyright:
    © 2018 IEEE.

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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