Abstract
In this paper, we present a half-and-half compare contents addressable memory (HHC-CAM) to reduce the dynamic power consumption as well as white space between the cell array and peripheral. In the proposed HHC-CAM, by splitting the match-line (ML), almost 99% of entries are filtered out in first half-side comparison. Thanks to the reduced ML switching capacitance, 42% lower energy delay product (EDP) is achieved compared to the conventional selective precharge approach. The proposed 16KB, 10T-NOR CAM macro, has been fabricated in a 14nm FinFET technology, and the chip measurement results show the energy consumption of 0.38fJ/search/bit (560ps search delay), which is the best EDP reported in literature.
Original language | English |
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Title of host publication | 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 17-18 |
Number of pages | 2 |
ISBN (Electronic) | 9781538667002 |
DOIs | |
Publication status | Published - 2018 Oct 22 |
Event | 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States Duration: 2018 Jun 18 → 2018 Jun 22 |
Publication series
Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Volume | 2018-June |
Other
Other | 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 |
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Country/Territory | United States |
City | Honolulu |
Period | 18/6/18 → 18/6/22 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering