Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP

Heemin Lee; Sungyeong Jang; Han Yee Kim; Taeweon Suh

doi:10.1109/icoin50884.2021.9334005

Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP

Heemin Lee, Sungyeong Jang, Han Yee Kim, Taeweon Suh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Cache side-channel attacks have been getting remarked as it threatens the information security of the multitenant systems. Among them, the FLUSH+RELOAD attack is one of the high-accuracy and high-resolution cache side-channel attacks. However, there have been few works targeting Arm architecture due to its architectural differences from x86 processors such as accessibility of cache flush instruction. In this paper, we design hardware that allows unprivileged cache invalidation on Arm processor through ACP. By utilizing the developed IP, we demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode. Our suggestion shows better performance than previous studies using cache flush instruction.

Original language	English
Title of host publication	35th International Conference on Information Networking, ICOIN 2021
Publisher	IEEE Computer Society
Pages	32-35
Number of pages	4
ISBN (Electronic)	9781728191003
DOIs	https://doi.org/10.1109/icoin50884.2021.9334005
Publication status	Published - 2021 Jan 13
Event	35th International Conference on Information Networking, ICOIN 2021 - Jeju Island, Korea, Republic of Duration: 2021 Jan 13 → 2021 Jan 16

Publication series

Name	International Conference on Information Networking
Volume	2021-January
ISSN (Print)	1976-7684

Conference

Conference	35th International Conference on Information Networking, ICOIN 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/1/13 → 21/1/16

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

ACP
Arm
Cache side-channel attacks
and FPGA

ASJC Scopus subject areas

Computer Networks and Communications
Information Systems

Access to Document

10.1109/icoin50884.2021.9334005

Cite this

Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP. / Lee, Heemin; Jang, Sungyeong; Kim, Han Yee et al.
35th International Conference on Information Networking, ICOIN 2021. IEEE Computer Society, 2021. p. 32-35 9334005 (International Conference on Information Networking; Vol. 2021-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, H, Jang, S, Kim, HY & Suh, T 2021, Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP. in 35th International Conference on Information Networking, ICOIN 2021., 9334005, International Conference on Information Networking, vol. 2021-January, IEEE Computer Society, pp. 32-35, 35th International Conference on Information Networking, ICOIN 2021, Jeju Island, Korea, Republic of, 21/1/13. https://doi.org/10.1109/icoin50884.2021.9334005

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title = "Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP",

abstract = "Cache side-channel attacks have been getting remarked as it threatens the information security of the multitenant systems. Among them, the FLUSH+RELOAD attack is one of the high-accuracy and high-resolution cache side-channel attacks. However, there have been few works targeting Arm architecture due to its architectural differences from x86 processors such as accessibility of cache flush instruction. In this paper, we design hardware that allows unprivileged cache invalidation on Arm processor through ACP. By utilizing the developed IP, we demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode. Our suggestion shows better performance than previous studies using cache flush instruction.",

keywords = "ACP, Arm, Cache side-channel attacks, and FPGA",

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AB - Cache side-channel attacks have been getting remarked as it threatens the information security of the multitenant systems. Among them, the FLUSH+RELOAD attack is one of the high-accuracy and high-resolution cache side-channel attacks. However, there have been few works targeting Arm architecture due to its architectural differences from x86 processors such as accessibility of cache flush instruction. In this paper, we design hardware that allows unprivileged cache invalidation on Arm processor through ACP. By utilizing the developed IP, we demonstrate a FLUSH+RELOAD attack on T table-based AES in unprivileged user mode. Our suggestion shows better performance than previous studies using cache flush instruction.

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Hardware-Based FLUSH+RELOAD Attack on Armv8 System via ACP

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this