Abstract
Graph convolutional network (GCN), which first applies convolutional operations to process graph data, has gained attention in various tasks involving relational data. Previous GCN accelerators have been designed with heterogeneous cores, considering two stages of inference (aggregation and combination), or with a unified core based on the inference of multi-layer as an iterative sparse-dense matrix multiplication. However, those prior works have suffered from an unnecessary large number of multiply-accumulate (MAC) operations and/or main memory accesses. In this paper, we propose HeNCoG, a GCN accelerator that utilizes a heterogeneous MAC array core for the combination stage and a near-memory computing core for the aggregation stage. In HeNCoG, considering that the number of MAC operations is significantly reduced when changing the stage execution order, the combination stage is executed first with a row-stationary dataflow. In the aggregation stage, magneto-resistive random-access memory (MRAM)-based near-memory computing is employed to reduce the number of main memory accesses needed to access the adjacency matrix in the graph dataset. Graph partitioning and double buffering techniques are also applied to further improve hardware efficiencies. Simulation results show that the HeNCoG architecture reduces execution cycles by 97% and memory accesses by 42% compared to previous works.
Original language | English |
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Title of host publication | ISCAS 2024 - IEEE International Symposium on Circuits and Systems |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9798350330991 |
DOIs | |
Publication status | Published - 2024 |
Event | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 - Singapore, Singapore Duration: 2024 May 19 → 2024 May 22 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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ISSN (Print) | 0271-4310 |
Conference
Conference | 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 |
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Country/Territory | Singapore |
City | Singapore |
Period | 24/5/19 → 24/5/22 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- Domain Specific Accelerator
- Graph Convolutional Network
- Near-memory Computing
- Sparse Matrix Multiplication
ASJC Scopus subject areas
- Electrical and Electronic Engineering