TY - JOUR
T1 - Heterogeneous SRAM cell sizing for low-power H.264 applications
AU - Kwon, Jinmo
AU - Chang, Ik Joon
AU - Lee, Insoo
AU - Park, Heemin
AU - Park, Jongsun
N1 - Funding Information:
Manuscript received March 01, 2011; revised July 12, 2011 and October 12, 2011; accepted November 24, 2011. Date of publication February 14, 2012; date of current version September 25, 2012. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science, and Technology (2010-0004484). This paper was recommended by Associate Editor C.-C. Wang.
PY - 2012
Y1 - 2012
N2 - In low-voltage operation, static random-access memory (SRAM) bit-cells suffer from large failure probabilities with technology scaling. With the increasing failures, conventional SRAM memory is still designed without considering the importance differences found among the data stored in the SRAM bit-cells. This paper presents a heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. As a result, the failure probabilities significantly decrease for the SRAM cells storing the more important bits, which allows us to obtain the better video quality even in lower voltage operation. In order to find the SRAM bit-cell sizes that achieve the best video quality under SRAM area constraint, we propose a heterogeneous SRAM sizing algorithm based on a dynamic programming. Compared to the brute-force search, the proposed algorithm greatly reduces the computation time needed to select the SRAM bit-cell sizes of 8 bit pixel. Experimental results show that under iso-area condition, the heterogeneous SRAM array achieves significant PSNR improvements (average 4.49 dB at 900-mV operation) compared to the conventional one with identical cell sizing.
AB - In low-voltage operation, static random-access memory (SRAM) bit-cells suffer from large failure probabilities with technology scaling. With the increasing failures, conventional SRAM memory is still designed without considering the importance differences found among the data stored in the SRAM bit-cells. This paper presents a heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. As a result, the failure probabilities significantly decrease for the SRAM cells storing the more important bits, which allows us to obtain the better video quality even in lower voltage operation. In order to find the SRAM bit-cell sizes that achieve the best video quality under SRAM area constraint, we propose a heterogeneous SRAM sizing algorithm based on a dynamic programming. Compared to the brute-force search, the proposed algorithm greatly reduces the computation time needed to select the SRAM bit-cell sizes of 8 bit pixel. Experimental results show that under iso-area condition, the heterogeneous SRAM array achieves significant PSNR improvements (average 4.49 dB at 900-mV operation) compared to the conventional one with identical cell sizing.
KW - H.264 systems
KW - SRAM bit-cell
KW - low-power static random-access memory (SRAM)
UR - http://www.scopus.com/inward/record.url?scp=84867333478&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2012.2185335
DO - 10.1109/TCSI.2012.2185335
M3 - Article
AN - SCOPUS:84867333478
SN - 1549-8328
VL - 59
SP - 2275
EP - 2284
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 10
M1 - 6152179
ER -