Heterogeneous SRAM cell sizing for low-power H.264 applications

Jinmo Kwon, Ik Joon Chang, Insoo Lee, Heemin Park, Jongsun Park

Research output: Contribution to journalArticlepeer-review

42 Citations (Scopus)


In low-voltage operation, static random-access memory (SRAM) bit-cells suffer from large failure probabilities with technology scaling. With the increasing failures, conventional SRAM memory is still designed without considering the importance differences found among the data stored in the SRAM bit-cells. This paper presents a heterogeneous SRAM sizing approach for the embedded memory of H.264 video processor, where the more important higher order data bits are stored in the relatively larger SRAM bit-cells and the less important bits are stored in the smaller ones. As a result, the failure probabilities significantly decrease for the SRAM cells storing the more important bits, which allows us to obtain the better video quality even in lower voltage operation. In order to find the SRAM bit-cell sizes that achieve the best video quality under SRAM area constraint, we propose a heterogeneous SRAM sizing algorithm based on a dynamic programming. Compared to the brute-force search, the proposed algorithm greatly reduces the computation time needed to select the SRAM bit-cell sizes of 8 bit pixel. Experimental results show that under iso-area condition, the heterogeneous SRAM array achieves significant PSNR improvements (average 4.49 dB at 900-mV operation) compared to the conventional one with identical cell sizing.

Original languageEnglish
Article number6152179
Pages (from-to)2275-2284
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number10
Publication statusPublished - 2012


  • H.264 systems
  • SRAM bit-cell
  • low-power static random-access memory (SRAM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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