TY - GEN
T1 - Hierarchical data structure-based timing controller design for plasma display panels
AU - Na, Yeoul
AU - Hwang, Seok Joong
AU - Bak, Giseong
AU - Kim, Seon Wook
AU - Lee, Cheol Ho
AU - Min, Junkyu
AU - Kim, Taejin
PY - 2010
Y1 - 2010
N2 - In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our prototype system runs at 83 MHz on Spartan-3A DSP FPGA, and the new design achieves the reduction of 73% in resource usage from the previous implementation.
AB - In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our prototype system runs at 83 MHz on Spartan-3A DSP FPGA, and the new design achieves the reduction of 73% in resource usage from the previous implementation.
UR - http://www.scopus.com/inward/record.url?scp=77956003340&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956003340&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537616
DO - 10.1109/ISCAS.2010.5537616
M3 - Conference contribution
AN - SCOPUS:77956003340
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 4121
EP - 4124
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -