Hierarchical data structure-based timing controller design for plasma display panels

Yeoul Na, Seok Joong Hwang, Giseong Bak, Seon Wook Kim, Cheol Ho Lee, Junkyu Min, Taejin Kim

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    In this paper, we propose a timing controller design to use a hierarchical structure of control signals for plasma display panels (PDPs). Also, we used a double buffering and a repeatable FIFO in order to reduce the workload of memory accesses for control data, and provided a graphical user interface program for easy control data management. Our prototype system runs at 83 MHz on Spartan-3A DSP FPGA, and the new design achieves the reduction of 73% in resource usage from the previous implementation.

    Original languageEnglish
    Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
    Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
    Pages4121-4124
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
    Duration: 2010 May 302010 Jun 2

    Publication series

    NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

    Other

    Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
    Country/TerritoryFrance
    CityParis
    Period10/5/3010/6/2

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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