With the aggressive scaling of DRAM process technology, the reliability degradation has become a critical issue, which inevitably increases the demand for more powerful error correction code (ECC) than conventional Hamming code. Although double error correction (DEC) BCH code needs less parity bits than other DEC codes, it cannot detect the errors larger than 3 bits. In this paper, we present a novel BCH code combined with cyclic redundancy check (CRC) code which can effectively detect multi-bit errors. By employing the CRC code, the proposed BCH code corrects double errors with a 3-bit error detection probability of 84%. In addition, by reusing the BCH encoder as CRC encoder and decoder in the proposed BCH, the area overhead of the proposed BCH is only 7.8% compared to the conventional BCH code.
|Title of host publication||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of|
Duration: 2022 Oct 19 → 2022 Oct 22
|Name||Proceedings - International SoC Design Conference 2022, ISOCC 2022|
|Conference||19th International System-on-Chip Design Conference, ISOCC 2022|
|Country/Territory||Korea, Republic of|
|Period||22/10/19 → 22/10/22|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.
© 2022 IEEE.
- BCH Code
- Error Correction Code
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Science Applications
- Hardware and Architecture
- Safety, Risk, Reliability and Quality