High Detection Rate BCH Code with CRC Code for Memory Application

Minseo Kim; Jongsun Park

doi:10.1109/ISOCC56007.2022.10031579

High Detection Rate BCH Code with CRC Code for Memory Application

Minseo Kim, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

With the aggressive scaling of DRAM process technology, the reliability degradation has become a critical issue, which inevitably increases the demand for more powerful error correction code (ECC) than conventional Hamming code. Although double error correction (DEC) BCH code needs less parity bits than other DEC codes, it cannot detect the errors larger than 3 bits. In this paper, we present a novel BCH code combined with cyclic redundancy check (CRC) code which can effectively detect multi-bit errors. By employing the CRC code, the proposed BCH code corrects double errors with a 3-bit error detection probability of 84%. In addition, by reusing the BCH encoder as CRC encoder and decoder in the proposed BCH, the area overhead of the proposed BCH is only 7.8% compared to the conventional BCH code.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2022, ISOCC 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	35-36
Number of pages	2
ISBN (Electronic)	9781665459716
DOIs	https://doi.org/10.1109/ISOCC56007.2022.10031579
Publication status	Published - 2022
Event	19th International System-on-Chip Design Conference, ISOCC 2022 - Gangneung-si, Korea, Republic of Duration: 2022 Oct 19 → 2022 Oct 22

Publication series

Name	Proceedings - International SoC Design Conference 2022, ISOCC 2022

Conference

Conference	19th International System-on-Chip Design Conference, ISOCC 2022
Country/Territory	Korea, Republic of
City	Gangneung-si
Period	22/10/19 → 22/10/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

BCH Code
DRAM
Error Correction Code

ASJC Scopus subject areas

Artificial Intelligence
Computer Science Applications
Hardware and Architecture
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISOCC56007.2022.10031579

Cite this

High Detection Rate BCH Code with CRC Code for Memory Application. / Kim, Minseo; Park, Jongsun.
Proceedings - International SoC Design Conference 2022, ISOCC 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 35-36 (Proceedings - International SoC Design Conference 2022, ISOCC 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, M & Park, J 2022, High Detection Rate BCH Code with CRC Code for Memory Application. in Proceedings - International SoC Design Conference 2022, ISOCC 2022. Proceedings - International SoC Design Conference 2022, ISOCC 2022, Institute of Electrical and Electronics Engineers Inc., pp. 35-36, 19th International System-on-Chip Design Conference, ISOCC 2022, Gangneung-si, Korea, Republic of, 22/10/19. https://doi.org/10.1109/ISOCC56007.2022.10031579

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title = "High Detection Rate BCH Code with CRC Code for Memory Application",

abstract = "With the aggressive scaling of DRAM process technology, the reliability degradation has become a critical issue, which inevitably increases the demand for more powerful error correction code (ECC) than conventional Hamming code. Although double error correction (DEC) BCH code needs less parity bits than other DEC codes, it cannot detect the errors larger than 3 bits. In this paper, we present a novel BCH code combined with cyclic redundancy check (CRC) code which can effectively detect multi-bit errors. By employing the CRC code, the proposed BCH code corrects double errors with a 3-bit error detection probability of 84%. In addition, by reusing the BCH encoder as CRC encoder and decoder in the proposed BCH, the area overhead of the proposed BCH is only 7.8% compared to the conventional BCH code.",

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series = "Proceedings - International SoC Design Conference 2022, ISOCC 2022",

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AB - With the aggressive scaling of DRAM process technology, the reliability degradation has become a critical issue, which inevitably increases the demand for more powerful error correction code (ECC) than conventional Hamming code. Although double error correction (DEC) BCH code needs less parity bits than other DEC codes, it cannot detect the errors larger than 3 bits. In this paper, we present a novel BCH code combined with cyclic redundancy check (CRC) code which can effectively detect multi-bit errors. By employing the CRC code, the proposed BCH code corrects double errors with a 3-bit error detection probability of 84%. In addition, by reusing the BCH encoder as CRC encoder and decoder in the proposed BCH, the area overhead of the proposed BCH is only 7.8% compared to the conventional BCH code.

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High Detection Rate BCH Code with CRC Code for Memory Application

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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