High performance and area-efficient circuit-switched network on chip design

Phi Hung Pham; Yogendera Kumar; Chulwoo Kim

doi:10.1109/CIT.2006.97

High performance and area-efficient circuit-switched network on chip design

Phi Hung Pham, Yogendera Kumar, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

High performance and area-efficient circuit-switched on chip network using 4×4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18μm process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.

Original language	English
Title of host publication	Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006
DOIs	https://doi.org/10.1109/CIT.2006.97
Publication status	Published - 2006
Event	6th IEEE International Conference on Computer and Information Technology, CIT 2006 - Seoul, Korea, Republic of Duration: 2006 Sept 20 → 2006 Sept 22

Publication series

Name	Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006

Other

Other	6th IEEE International Conference on Computer and Information Technology, CIT 2006
Country/Territory	Korea, Republic of
City	Seoul
Period	06/9/20 → 06/9/22

ASJC Scopus subject areas

Computer Science Applications
Information Systems
Software
Mathematics(all)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/CIT.2006.97

Cite this

Pham, P. H., Kumar, Y., & Kim, C. (2006). High performance and area-efficient circuit-switched network on chip design. In Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006 Article 4020005 (Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006). https://doi.org/10.1109/CIT.2006.97

High performance and area-efficient circuit-switched network on chip design. / Pham, Phi Hung; Kumar, Yogendera; Kim, Chulwoo.
Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006. 2006. 4020005 (Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Pham, PH, Kumar, Y & Kim, C 2006, High performance and area-efficient circuit-switched network on chip design. in Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006., 4020005, Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006, 6th IEEE International Conference on Computer and Information Technology, CIT 2006, Seoul, Korea, Republic of, 06/9/20. https://doi.org/10.1109/CIT.2006.97

@inproceedings{aae6fea9d8dc40559e03ed013ad2910f,

title = "High performance and area-efficient circuit-switched network on chip design",

abstract = "High performance and area-efficient circuit-switched on chip network using 4×4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18μm process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.",

author = "Pham, {Phi Hung} and Yogendera Kumar and Chulwoo Kim",

year = "2006",

doi = "10.1109/CIT.2006.97",

language = "English",

isbn = "076952687X",

series = "Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006",

booktitle = "Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006",

note = "6th IEEE International Conference on Computer and Information Technology, CIT 2006 ; Conference date: 20-09-2006 Through 22-09-2006",

}

TY - GEN

T1 - High performance and area-efficient circuit-switched network on chip design

AU - Pham, Phi Hung

AU - Kumar, Yogendera

AU - Kim, Chulwoo

PY - 2006

Y1 - 2006

N2 - High performance and area-efficient circuit-switched on chip network using 4×4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18μm process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.

AB - High performance and area-efficient circuit-switched on chip network using 4×4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18μm process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.

UR - http://www.scopus.com/inward/record.url?scp=34547339142&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547339142&partnerID=8YFLogxK

U2 - 10.1109/CIT.2006.97

DO - 10.1109/CIT.2006.97

M3 - Conference contribution

AN - SCOPUS:34547339142

SN - 076952687X

SN - 9780769526874

T3 - Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006

BT - Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006

T2 - 6th IEEE International Conference on Computer and Information Technology, CIT 2006

Y2 - 20 September 2006 through 22 September 2006

ER -

High performance and area-efficient circuit-switched network on chip design

Abstract

Publication series

Other

ASJC Scopus subject areas

UN SDGs

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