High performance and area-efficient circuit-switched network on chip design

Phi Hung Pham; Yogendera Kumar; Chulwoo Kim

doi:10.1109/CIT.2006.97

High performance and area-efficient circuit-switched network on chip design

Phi Hung Pham^*
, Yogendera Kumar
, Chulwoo Kim

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

High performance and area-efficient circuit-switched on chip network using 4×4 folded torus topology with simple router architecture and circuit setup scheme is presented. When designed (synthesized and simulated) and analyzed for performance in 0.18μm process technology, the pre-layout area of each router is found to be 0.018 mm2 and the minimum probing period as 2.2 ns. The proposed NoC supports the wave-pipelining transmission across multi-clock domain environment to achieve the high throughput and energy efficiency.

Original language	English
Title of host publication	Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006
DOIs	https://doi.org/10.1109/CIT.2006.97
Publication status	Published - 2006
Event	6th IEEE International Conference on Computer and Information Technology, CIT 2006 - Seoul, Korea, Republic of Duration: 2006 Sept 20 → 2006 Sept 22

Publication series

Name	Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006

Other

Other	6th IEEE International Conference on Computer and Information Technology, CIT 2006
Country/Territory	Korea, Republic of
City	Seoul
Period	06/9/20 → 06/9/22

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

ASJC Scopus subject areas

Computer Science Applications
Information Systems
Software
General Mathematics

Access to Document

10.1109/CIT.2006.97

Cite this

Pham, P. H., Kumar, Y., & Kim, C. (2006). High performance and area-efficient circuit-switched network on chip design. In Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006 Article 4020005 (Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006). https://doi.org/10.1109/CIT.2006.97

High performance and area-efficient circuit-switched network on chip design. / Pham, Phi Hung; Kumar, Yogendera; Kim, Chulwoo.
Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006. 2006. 4020005 (Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Pham, PH, Kumar, Y & Kim, C 2006, High performance and area-efficient circuit-switched network on chip design. in Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006., 4020005, Proceedings - Sixth IEEE International Conference on Computer and Information Technology, CIT 2006, 6th IEEE International Conference on Computer and Information Technology, CIT 2006, Seoul, Korea, Republic of, 06/9/20. https://doi.org/10.1109/CIT.2006.97

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High performance and area-efficient circuit-switched network on chip design

Abstract

Publication series

Other

UN SDGs

ASJC Scopus subject areas

Access to Document

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