High performance CMOS dual-modulus prescaler using selective latch technique

Se Yeob Kim; Soon Seob Lee; Soo-Won Kim; Tae Geun Kim

doi:10.1109/ICVC.1999.820919

High performance CMOS dual-modulus prescaler using selective latch technique

Se Yeob Kim, Soon Seob Lee, Soo-Won Kim, Tae Geun Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

Original language	English
Title of host publication	ICVC 1999 - 6th International Conference on VLSI and CAD
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	321-324
Number of pages	4
ISBN (Print)	0780357272, 9780780357273
DOIs	https://doi.org/10.1109/ICVC.1999.820919
Publication status	Published - 1999 Jan 1
Event	6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of Duration: 1999 Oct 26 → 1999 Oct 27

Other

Other	6th International Conference on VLSI and CAD, ICVC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	99/10/26 → 99/10/27

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ICVC.1999.820919

Cite this

Kim, SY, Lee, SS, Kim, S-W & Kim, TG 1999, High performance CMOS dual-modulus prescaler using selective latch technique. in ICVC 1999 - 6th International Conference on VLSI and CAD., 820919, Institute of Electrical and Electronics Engineers Inc., pp. 321-324, 6th International Conference on VLSI and CAD, ICVC 1999, Seoul, Korea, Republic of, 99/10/26. https://doi.org/10.1109/ICVC.1999.820919

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abstract = "This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.",

author = "Kim, {Se Yeob} and Lee, {Soon Seob} and Soo-Won Kim and Kim, {Tae Geun}",

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N2 - This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

AB - This paper describes an improved CMOS dual-modulus prescaler (DMP) using selective latch technique for RF mobile communication systems. This technique enables high speed operation at reduced power consumption, which is obtained by reducing the number of full speed operating flip-flops as well as the number of logic gates. Moreover, the proposed DMP demonstrates control signal immunity from propagation delay which is known to cause the critical error in asynchronous DMP architectures. Simulation results, employing 0.35 μm CMOS technology, demonstrate 2.6 GHz maximum operating frequency at 2.7 V power supply and 22.6 mW power consumption.

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SN - 9780780357273

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High performance CMOS dual-modulus prescaler using selective latch technique

Abstract

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