Abstract
Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-μm technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.
Original language | English |
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Pages (from-to) | 244-253 |
Number of pages | 10 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 11 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2003 Apr |
Externally published | Yes |
Keywords
- Computation sharing
- Computation sharing multiplier
- High-performance finite impulse response (FIR) filter
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering