Abstract
This paper presents S2L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S2L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility.
Original language | English |
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Pages | 59-64 |
Number of pages | 6 |
Publication status | Published - 2000 |
Externally published | Yes |
Event | 2000 International Conference on Computer Design - Austin, TX, USA Duration: 2000 Sept 17 → 2000 Sept 20 |
Other
Other | 2000 International Conference on Computer Design |
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City | Austin, TX, USA |
Period | 00/9/17 → 00/9/20 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering