High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

Chulwoo Kim; Seong Ook Jung; Kwang Hyun Baek; Sung Mo Kang

doi:10.1109/TCSII.2002.802960

High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

Chulwoo Kim, Seong Ook Jung, Kwang Hyun Baek, Sung Mo Kang

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.

Original language	English
Pages (from-to)	434-439
Number of pages	6
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	49
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2002.802960
Publication status	Published - 2002 Jun
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received July 2, 2000; revised May 28, 2002. This work was supported in part by Semiconductor Research Corp. under Grant SRC 98-HJ-641. This paper was recommended by Associate Editor X. Sung.

Keywords

Adder
Dynamic logic
Low-power
Skewed logic

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2002.802960

Cite this

@article{e27207c06cc7479fbd3b9e5bd18759b9,

title = "High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic",

abstract = "In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.",

keywords = "Adder, Dynamic logic, Low-power, Skewed logic",

author = "Chulwoo Kim and Jung, {Seong Ook} and Baek, {Kwang Hyun} and Kang, {Sung Mo}",

note = "Funding Information: Manuscript received July 2, 2000; revised May 28, 2002. This work was supported in part by Semiconductor Research Corp. under Grant SRC 98-HJ-641. This paper was recommended by Associate Editor X. Sung.",

year = "2002",

month = jun,

doi = "10.1109/TCSII.2002.802960",

language = "English",

volume = "49",

pages = "434--439",

journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",

issn = "1057-7130",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

AU - Kim, Chulwoo

AU - Jung, Seong Ook

AU - Baek, Kwang Hyun

AU - Kang, Sung Mo

N1 - Funding Information: Manuscript received July 2, 2000; revised May 28, 2002. This work was supported in part by Semiconductor Research Corp. under Grant SRC 98-HJ-641. This paper was recommended by Associate Editor X. Sung.

PY - 2002/6

Y1 - 2002/6

N2 - In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.

AB - In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed without charge sharing problem. PDL uses only parallel-connected transistors for fast logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles, which use stacked transistors. Furthermore, PDL needs no signal ordering or tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without the usual area penalty due to logic duplication. Our experimental results on two 32-bit carry lookahead adders using 0.25-μm CMOS technology show that PDL with speed-enhanced skewed static (SSS) logic reduces the delay over clock-delayed(CD)-domino by 15%-27% and the power-delay product by 20%-37%.

KW - Adder

KW - Dynamic logic

KW - Low-power

KW - Skewed logic

UR - http://www.scopus.com/inward/record.url?scp=0036624650&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2002.802960

DO - 10.1109/TCSII.2002.802960

M3 - Article

AN - SCOPUS:0036624650

SN - 1057-7130

VL - 49

SP - 434

EP - 439

JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

IS - 6

ER -

High-speed CMOS circuits with parallel dynamic logic and speed-enhanced skewed static logic

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this