Abstract
This paper presents a high-speed hardware architecture of an improved Givens rotation-based QR decomposition, named tournament-based complex Givens rotation (T-CGR). In the proposed approach, more than one pivots are selected and zero-insertion processes of Givens-rotations are performed in parallel like tournament in order to increase the throughput. As a result, the QR decomposition performance significantly increases compared to the triangular systolic array (TSA) approach. Moreover, the circuit area was reduced due to the smaller number of flip-flops for holding the computed results during the decomposition process. The proposed QR decomposition hardware was implemented using TSMC 0.25 um technology. The experimental results show that the proposed architecture achieves 73.00% speed-up over the TACR/TSA-based architecture for the 8 × 8 matrix decomposition.
Original language | English |
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Pages | 21-24 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2012 |
Event | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 2012 May 20 → 2012 May 23 |
Other
Other | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 12/5/20 → 12/5/23 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering