Abstract
In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.
Original language | English |
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Article number | 2931410 |
Pages (from-to) | 1362-1365 |
Number of pages | 4 |
Journal | IEEE Electron Device Letters |
Volume | 40 |
Issue number | 9 |
DOIs | |
Publication status | Published - 2019 Sept |
Bibliographical note
Publisher Copyright:0741-3106 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
Keywords
- Epitaxial lift-off
- Ge MOSFETs
- Ge-OI
- Ge-on-Insulator
- Junctionless MOSFETs
- Wafer bonding
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering