Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Hyeong Rak Lim, Seong Kwang Kim, Jae Hoon Han, Hansung Kim, Dae Myeong Geum, Yun Joong Lee, Byeong Kwon Ju, Hyung Jun Kim, Sanghyeon Kim

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.

Original languageEnglish
Article number2931410
Pages (from-to)1362-1365
Number of pages4
JournalIEEE Electron Device Letters
Issue number9
Publication statusPublished - 2019 Sept

Bibliographical note

Funding Information:
Manuscript received June 27, 2019; revised July 12, 2019, July 18, 2019 and July 19, 2019; accepted July 20, 2019. Date of publication July 26, 2019; date of current version August 23, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) under Grant 2015004870 and Grant 2016910562, in part by the Future Semiconductor Device Technology Development Program under MOTIE (Ministry of Trade, Industry and Energy) under Grant 10052962, in part by the Korea Advanced Institute of Science and Technology (KAIST) startup funding under Grant G 04180061, and in part by the Brain Korea21plus (BK21plus). The review of this letter was arranged by Editor S. Hall. (Corresponding author: Sanghyeon Kim.) H.-R. Lim is with the Display and Nanosystem Laboratory, School of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea.

Publisher Copyright:
0741-3106 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.


  • Epitaxial lift-off
  • Ge MOSFETs
  • Ge-OI
  • Ge-on-Insulator
  • Junctionless MOSFETs
  • Wafer bonding

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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