Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Hyeong Rak Lim; Seong Kwang Kim; Jae Hoon Han; Hansung Kim; Dae Myeong Geum; Yun Joong Lee; Byeong Kwon Ju; Hyung Jun Kim; Sanghyeon Kim

doi:10.1109/LED.2019.2931410

Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Hyeong Rak Lim, Seong Kwang Kim, Jae Hoon Han, Hansung Kim, Dae Myeong Geum, Yun Joong Lee, Byeong Kwon Ju, Hyung Jun Kim, Sanghyeon Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µ_eff) of 160 cm²/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher V_th tunability and improvement of µ_eff by bottom-gate biasing.

Original language	English
Article number	2931410
Pages (from-to)	1362-1365
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	9
DOIs	https://doi.org/10.1109/LED.2019.2931410
Publication status	Published - 2019 Sept

Bibliographical note

Funding Information:
Manuscript received June 27, 2019; revised July 12, 2019, July 18, 2019 and July 19, 2019; accepted July 20, 2019. Date of publication July 26, 2019; date of current version August 23, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) under Grant 2015004870 and Grant 2016910562, in part by the Future Semiconductor Device Technology Development Program under MOTIE (Ministry of Trade, Industry and Energy) under Grant 10052962, in part by the Korea Advanced Institute of Science and Technology (KAIST) startup funding under Grant G 04180061, and in part by the Brain Korea21plus (BK21plus). The review of this letter was arranged by Editor S. Hall. (Corresponding author: Sanghyeon Kim.) H.-R. Lim is with the Display and Nanosystem Laboratory, School of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea.

Publisher Copyright:
0741-3106 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

Keywords

Epitaxial lift-off
Ge MOSFETs
Ge-OI
Ge-on-Insulator
Junctionless MOSFETs
Wafer bonding

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2019.2931410

Cite this

@article{8c908c746e1845b2b6e6b0fca73fa94d,

title = "Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs",

abstract = "In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.",

keywords = "Epitaxial lift-off, Ge MOSFETs, Ge-OI, Ge-on-Insulator, Junctionless MOSFETs, Wafer bonding",

author = "Lim, {Hyeong Rak} and Kim, {Seong Kwang} and Han, {Jae Hoon} and Hansung Kim and Geum, {Dae Myeong} and Lee, {Yun Joong} and Ju, {Byeong Kwon} and Kim, {Hyung Jun} and Sanghyeon Kim",

note = "Funding Information: Manuscript received June 27, 2019; revised July 12, 2019, July 18, 2019 and July 19, 2019; accepted July 20, 2019. Date of publication July 26, 2019; date of current version August 23, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) under Grant 2015004870 and Grant 2016910562, in part by the Future Semiconductor Device Technology Development Program under MOTIE (Ministry of Trade, Industry and Energy) under Grant 10052962, in part by the Korea Advanced Institute of Science and Technology (KAIST) startup funding under Grant G 04180061, and in part by the Brain Korea21plus (BK21plus). The review of this letter was arranged by Editor S. Hall. (Corresponding author: Sanghyeon Kim.) H.-R. Lim is with the Display and Nanosystem Laboratory, School of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea. Publisher Copyright: 0741-3106 {\textcopyright} 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.",

year = "2019",

month = sep,

doi = "10.1109/LED.2019.2931410",

language = "English",

volume = "40",

pages = "1362--1365",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

AU - Lim, Hyeong Rak

AU - Kim, Seong Kwang

AU - Han, Jae Hoon

AU - Kim, Hansung

AU - Geum, Dae Myeong

AU - Lee, Yun Joong

AU - Ju, Byeong Kwon

AU - Kim, Hyung Jun

AU - Kim, Sanghyeon

N1 - Funding Information: Manuscript received June 27, 2019; revised July 12, 2019, July 18, 2019 and July 19, 2019; accepted July 20, 2019. Date of publication July 26, 2019; date of current version August 23, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) under Grant 2015004870 and Grant 2016910562, in part by the Future Semiconductor Device Technology Development Program under MOTIE (Ministry of Trade, Industry and Energy) under Grant 10052962, in part by the Korea Advanced Institute of Science and Technology (KAIST) startup funding under Grant G 04180061, and in part by the Brain Korea21plus (BK21plus). The review of this letter was arranged by Editor S. Hall. (Corresponding author: Sanghyeon Kim.) H.-R. Lim is with the Display and Nanosystem Laboratory, School of Electrical Engineering, Korea University, Seoul 02841, South Korea, and also with the Korea Institute of Science and Technology (KIST), Seoul 02792, South Korea. Publisher Copyright: 0741-3106 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

PY - 2019/9

Y1 - 2019/9

N2 - In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.

AB - In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.

KW - Epitaxial lift-off

KW - Ge MOSFETs

KW - Ge-OI

KW - Ge-on-Insulator

KW - Junctionless MOSFETs

KW - Wafer bonding

UR - http://www.scopus.com/inward/record.url?scp=85083680964&partnerID=8YFLogxK

U2 - 10.1109/LED.2019.2931410

DO - 10.1109/LED.2019.2931410

M3 - Article

AN - SCOPUS:85083680964

SN - 0741-3106

VL - 40

SP - 1362

EP - 1365

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 9

M1 - 2931410

ER -

Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this