Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Hyeong Rak Lim; Seong Kwang Kim; Jae Hoon Han; Hansung Kim; Dae Myeong Geum; Yun Joong Lee; Byeong Kwon Ju; Hyung Jun Kim; Sanghyeon Kim

doi:10.1109/LED.2019.2931410

Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Hyeong Rak Lim, Seong Kwang Kim, Jae Hoon Han, Hansung Kim, Dae Myeong Geum, Yun Joong Lee, Byeong Kwon Ju, Hyung Jun Kim, Sanghyeon Kim

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µ_eff) of 160 cm²/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher V_th tunability and improvement of µ_eff by bottom-gate biasing.

Original language	English
Article number	2931410
Pages (from-to)	1362-1365
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	9
DOIs	https://doi.org/10.1109/LED.2019.2931410
Publication status	Published - 2019 Sept

Bibliographical note

Publisher Copyright:
0741-3106 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

Keywords

Epitaxial lift-off
Ge MOSFETs
Ge-OI
Ge-on-Insulator
Junctionless MOSFETs
Wafer bonding

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2019.2931410

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title = "Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs",

abstract = "In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.",

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author = "Lim, {Hyeong Rak} and Kim, {Seong Kwang} and Han, {Jae Hoon} and Hansung Kim and Geum, {Dae Myeong} and Lee, {Yun Joong} and Ju, {Byeong Kwon} and Kim, {Hyung Jun} and Sanghyeon Kim",

note = "Publisher Copyright: 0741-3106 {\textcopyright} 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.",

year = "2019",

month = sep,

doi = "10.1109/LED.2019.2931410",

language = "English",

volume = "40",

pages = "1362--1365",

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AU - Lim, Hyeong Rak

AU - Kim, Seong Kwang

AU - Han, Jae Hoon

AU - Kim, Hansung

AU - Geum, Dae Myeong

AU - Lee, Yun Joong

AU - Ju, Byeong Kwon

AU - Kim, Hyung Jun

AU - Kim, Sanghyeon

PY - 2019/9

Y1 - 2019/9

N2 - In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.

AB - In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (µeff) of 160 cm2/V · s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of µeff by bottom-gate biasing.

KW - Epitaxial lift-off

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Impact of bottom-gate biasing on implant-free junctionless Ge-on-insulator n-MOSFETs

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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