Impact of using double-patterning versus single-patterning on threshold voltage (V_TH) variation in quasi-planar tri-gate bulk MOSFETs

To experimentally investigate the impact of double-patterning and double-etching (2P2E) versus single-patterning and single-etching (1P1E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage (V_TH) variation in a multigate bulk device, quasi-planar tri-gate (QPT) bulk metal-oxide semiconductor field-effect transistors (MOSFETs) are fabricated by a 28-nm complementary metal-oxide-semiconductor (CMOS) technology. It is experimentally verified that the LER profile obtained through using the 2P2E 193-nm immersion photolithography technique has a relatively longer correlation length (i.e., lower spatial frequency) than that by the 1P1E technique, although they have a comparable root-mean-square deviation and fractal dimension. By using Monte Carlo simulations to analyze the random V _TH variations in the QPT bulk MOSFETs, we confirm that the 2P2E-LER-induced V_TH variation (versus the 1P1E-LER-induced V _TH variation) is suppressed by ∼20\% in terms of σ (V _TH). However, the total V_TH variation in the QPT MOSFETs is slightly improved with the 2P2E technique, because the other variation sources such as random dopant fluctuation and work-function variation have still dominated the total V_TH variation. To fully benefit from the 2P2E technique, the other random/intrinsic variations should be better controlled in the QPT CMOS technology.