Implementation of H.264/AVC decoder for mobile video applications

Suh Ho Lee; Jeong Hun Kim; Ji Hwan Park; Seon Wook Kim; Suki Kim

Implementation of H.264/AVC decoder for mobile video applications

Suh Ho Lee^*
, Jeong Hun Kim
, Ji Hwan Park
, Seon Wook Kim
, Suki Kim

^*Corresponding author for this work

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an H.264/AVC baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 30 frames/sec with CIF_(352×288). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	5587-5590
Number of pages	4
Publication status	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 2006 May 21 → 2006 May 24

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	06/5/21 → 06/5/24

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Implementation of H.264/AVC decoder for mobile video applications. / Lee, Suh Ho; Kim, Jeong Hun; Park, Ji Hwan et al.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 5587-5590 1693901 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lee, SH, Kim, JH, Park, JH, Kim, SW & Kim, S 2006, Implementation of H.264/AVC decoder for mobile video applications. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693901, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 5587-5590, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 06/5/21.

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abstract = "This paper presents an H.264/AVC baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 30 frames/sec with CIF\_(352×288). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.",

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series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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AU - Kim, Suki

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Y1 - 2006

N2 - This paper presents an H.264/AVC baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 30 frames/sec with CIF_(352×288). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.

AB - This paper presents an H.264/AVC baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 30 frames/sec with CIF_(352×288). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.

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M3 - Conference contribution

AN - SCOPUS:34547363648

SN - 0780393902

SN - 9780780393905

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 5587

EP - 5590

BT - ISCAS 2006

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2006 through 24 May 2006

ER -

Implementation of H.264/AVC decoder for mobile video applications

Abstract

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ASJC Scopus subject areas

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