TY - GEN
T1 - Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification
AU - Cho, Junghoon
AU - Song, Junhyun
AU - Park, Jongsun
N1 - Funding Information:
This work was supported as part of Military Crypto Research Center (UD170109ED) funded by Defense Acquisition Program Administration (DAPA) and Agency for Defense Development (ADD).
Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/21
Y1 - 2020/10/21
N2 - Block cipher ARIA is a cryptography consists of similar algorithm structure with AES, which was proposed for obtaining both security and hardware efficiency. In this paper, ARIA architecture implemented with hardware optimization scheme is proposed, in order to meet the increasing demand of implementing cryptographic module with low hardware cost. To optimize the substitution layer, which is the largest component among ARIA architecture, areas of S-boxes are optimized with composite field extension and applying irreducible polynomial coefficients which minimizes hardware cost of S-boxes. Datapath through the substitution layer is modified from 128bit to 32bit to minimize the number of S-boxes which constitute the substitution layer. With these optimization schemes, proposed architecture is implemented and synthesized using 65nm CMOS process, obtained 9942 GE of hardware area which is 78.43% less than previous ARIA implementation work.
AB - Block cipher ARIA is a cryptography consists of similar algorithm structure with AES, which was proposed for obtaining both security and hardware efficiency. In this paper, ARIA architecture implemented with hardware optimization scheme is proposed, in order to meet the increasing demand of implementing cryptographic module with low hardware cost. To optimize the substitution layer, which is the largest component among ARIA architecture, areas of S-boxes are optimized with composite field extension and applying irreducible polynomial coefficients which minimizes hardware cost of S-boxes. Datapath through the substitution layer is modified from 128bit to 32bit to minimize the number of S-boxes which constitute the substitution layer. With these optimization schemes, proposed architecture is implemented and synthesized using 65nm CMOS process, obtained 9942 GE of hardware area which is 78.43% less than previous ARIA implementation work.
KW - ARIA
KW - Composite Field
KW - S-box
UR - http://www.scopus.com/inward/record.url?scp=85100756552&partnerID=8YFLogxK
U2 - 10.1109/ISOCC50952.2020.9332954
DO - 10.1109/ISOCC50952.2020.9332954
M3 - Conference contribution
AN - SCOPUS:85100756552
T3 - Proceedings - International SoC Design Conference, ISOCC 2020
SP - 304
EP - 305
BT - Proceedings - International SoC Design Conference, ISOCC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International System-on-Chip Design Conference, ISOCC 2020
Y2 - 21 October 2020 through 24 October 2020
ER -