Abstract
Block cipher ARIA is a cryptography consists of similar algorithm structure with AES, which was proposed for obtaining both security and hardware efficiency. In this paper, ARIA architecture implemented with hardware optimization scheme is proposed, in order to meet the increasing demand of implementing cryptographic module with low hardware cost. To optimize the substitution layer, which is the largest component among ARIA architecture, areas of S-boxes are optimized with composite field extension and applying irreducible polynomial coefficients which minimizes hardware cost of S-boxes. Datapath through the substitution layer is modified from 128bit to 32bit to minimize the number of S-boxes which constitute the substitution layer. With these optimization schemes, proposed architecture is implemented and synthesized using 65nm CMOS process, obtained 9942 GE of hardware area which is 78.43% less than previous ARIA implementation work.
Original language | English |
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Title of host publication | Proceedings - International SoC Design Conference, ISOCC 2020 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 304-305 |
Number of pages | 2 |
ISBN (Electronic) | 9781728183312 |
DOIs | |
Publication status | Published - 2020 Oct 21 |
Event | 17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24 |
Publication series
Name | Proceedings - International SoC Design Conference, ISOCC 2020 |
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Conference
Conference | 17th International System-on-Chip Design Conference, ISOCC 2020 |
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Country/Territory | Korea, Republic of |
City | Yeosu |
Period | 20/10/21 → 20/10/24 |
Bibliographical note
Publisher Copyright:© 2020 IEEE.
Keywords
- ARIA
- Composite Field
- S-box
ASJC Scopus subject areas
- Energy Engineering and Power Technology
- Electrical and Electronic Engineering
- Instrumentation
- Artificial Intelligence
- Hardware and Architecture