Implementation of monolithic 3D integrated TiO_x memristor-based neural network for high-performance in-memory computing

The monolithic three-dimensional (M3D) integration of memristor arrays with silicon transistors facilitates energy-efficient parallel data processing and attains high-density arrays, representing a breakthrough approach for in-memory computing systems. In this study, we designed and fabricated a 1-kbit M3D integration of TiO_x memristor (1 M) and the transmission gate-inverter circuit comprising of four MOSFETs as a transistor-selector (1TS), confirming both operational voltage range and current levels between 1 M and 1TS are well aligned. The designed 1TS efficiently eradicates voltage drops and substantially alleviates sneak current due to its high ON/OFF ratio of 7.18 × 10⁷, providing robust binary inputs with lower power consumption. Essential synaptic functions for 1-kbit 1 M and 1TS-1M arrays were validated, demonstrating consistent and robust LTP and LTD functions across 3000 pulses, with varying learning rates corresponding to the programming voltage schemes. Our 1-kbit 1TS-1M array architecture has the potential to be scaled to a 1.14 Tbit crossbar array without cell interference, becoming one of the largest M3D of memristor array configurations for in-memory computing and suggesting its capability to operate complex models. It demonstrates the viability of deploying a large-scale in-memory computing system efficient for accurately learning and recognizing complex tasks. This 1TS-1M array system achieved up to 79.47 % and 84.89 % recognition accuracies for the CIFAR-10 and UTK face images dataset, respectively, even in the limited convolution and pooling layers in the convolution neural network (CNN).