Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation

Woong Choi; Jongsun Park

doi:10.1109/TCAD.2016.2629446

Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation

Woong Choi, Jongsun Park

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is essential in SRAM design. In this paper, we propose an enhanced perturbation vector generation method to improve the accuracy of the yield estimation of the conventional direct SRAM yield computation method, which are access disturb margin (ADM) and write margin (WRM) first, by splitting the concave yield metric space, the estimation error caused by linear approximation can be significantly reduced with minor increase in simulation runtime. In addition, to compensate the inaccuracy of the conventional perturbation vector, a calibration method to reflect the multi-dc condition in SRAM assist operations is also proposed. Numerical results show that 37% improved estimation accuracy and 29% reduced estimation error can be achieved compared to the conventional ADM/WRM in the wide voltage range.

Original language	English
Article number	7745960
Pages (from-to)	1511-1521
Number of pages	11
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	36
Issue number	9
DOIs	https://doi.org/10.1109/TCAD.2016.2629446
Publication status	Published - 2017 Sept

Bibliographical note

Funding Information:
Manuscript received June 15, 2016; revised September 26, 2016; accepted November 1, 2016. Date of publication November 16, 2016; date of current version August 18, 2017. This work was supported in part by the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology (Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC) under Grant 10052716, and in part by the National Research Foundation of Korea under Grant NRF-2015M3D1A1070465 and Grant NRF-2016-R1A2B4015329. This paper was recommended by Associate Editor L.-C. Wang.

Publisher Copyright:
© 1982-2012 IEEE.

Keywords

Access disturb margin (ADM)
Monte Carlo
N-curve
SRAM
write margin (WRM)
yield

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2016.2629446

Cite this

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abstract = "Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is essential in SRAM design. In this paper, we propose an enhanced perturbation vector generation method to improve the accuracy of the yield estimation of the conventional direct SRAM yield computation method, which are access disturb margin (ADM) and write margin (WRM) first, by splitting the concave yield metric space, the estimation error caused by linear approximation can be significantly reduced with minor increase in simulation runtime. In addition, to compensate the inaccuracy of the conventional perturbation vector, a calibration method to reflect the multi-dc condition in SRAM assist operations is also proposed. Numerical results show that 37% improved estimation accuracy and 29% reduced estimation error can be achieved compared to the conventional ADM/WRM in the wide voltage range.",

keywords = "Access disturb margin (ADM), Monte Carlo, N-curve, SRAM, write margin (WRM), yield",

author = "Woong Choi and Jongsun Park",

note = "Funding Information: Manuscript received June 15, 2016; revised September 26, 2016; accepted November 1, 2016. Date of publication November 16, 2016; date of current version August 18, 2017. This work was supported in part by the Information Technology Research and Development Program of Korea Evaluation Institute of Industrial Technology (Design technology development of ultralow voltage operating circuit and IP for smart sensor SoC) under Grant 10052716, and in part by the National Research Foundation of Korea under Grant NRF-2015M3D1A1070465 and Grant NRF-2016-R1A2B4015329. This paper was recommended by Associate Editor L.-C. Wang. Publisher Copyright: {\textcopyright} 1982-2012 IEEE.",

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N2 - Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is essential in SRAM design. In this paper, we propose an enhanced perturbation vector generation method to improve the accuracy of the yield estimation of the conventional direct SRAM yield computation method, which are access disturb margin (ADM) and write margin (WRM) first, by splitting the concave yield metric space, the estimation error caused by linear approximation can be significantly reduced with minor increase in simulation runtime. In addition, to compensate the inaccuracy of the conventional perturbation vector, a calibration method to reflect the multi-dc condition in SRAM assist operations is also proposed. Numerical results show that 37% improved estimation accuracy and 29% reduced estimation error can be achieved compared to the conventional ADM/WRM in the wide voltage range.

AB - Accurate yield estimation under parametric variation is one of the most integral parts for robust and nonwasted circuit design. In particular, due to the significant impact of disparity on the high-replication circuit, precise yield estimation is essential in SRAM design. In this paper, we propose an enhanced perturbation vector generation method to improve the accuracy of the yield estimation of the conventional direct SRAM yield computation method, which are access disturb margin (ADM) and write margin (WRM) first, by splitting the concave yield metric space, the estimation error caused by linear approximation can be significantly reduced with minor increase in simulation runtime. In addition, to compensate the inaccuracy of the conventional perturbation vector, a calibration method to reflect the multi-dc condition in SRAM assist operations is also proposed. Numerical results show that 37% improved estimation accuracy and 29% reduced estimation error can be achieved compared to the conventional ADM/WRM in the wide voltage range.

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Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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