Improved vein pattern extracting algorithm and its implementation

Sang Kyun Im; Hyung Man Park; Soo Won Kim; Chang Kyung Chung; Hwan Soo Choi

doi:10.1109/ICCE.2000.854470

Improved vein pattern extracting algorithm and its implementation

Sang Kyun Im, Hyung Man Park, Soo Won Kim, Chang Kyung Chung, Hwan Soo Choi

* Honorary professors

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

This paper proposes an improved vein pattern extracting algorithm which compensates the loss of vein patterns in the edge area, gives more enhanced and stabilized vein pattern information, and shows better performance than the existing algorithm. Also, the problem arising from the iterative nature of filtering preprocess in the existing algorithm is solved by designing a filter that is processed only one time so that fast recognition speed and reduced hardware complexity is obtained. The proposed algorithm is implemented with a FPGA(Field Programmable Gate Array) device and the FAR(False Acceptance Rate) shows five times better than the existing algorithm and the recognition speed is measured to be 100[ms/person].

Original language	English
Pages (from-to)	2-3
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
DOIs	https://doi.org/10.1109/ICCE.2000.854470
Publication status	Published - 2000

ASJC Scopus subject areas

Industrial and Manufacturing Engineering
Electrical and Electronic Engineering

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10.1109/ICCE.2000.854470

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@article{7c79abcefc8c46f596b461848939d99f,

title = "Improved vein pattern extracting algorithm and its implementation",

abstract = "This paper proposes an improved vein pattern extracting algorithm which compensates the loss of vein patterns in the edge area, gives more enhanced and stabilized vein pattern information, and shows better performance than the existing algorithm. Also, the problem arising from the iterative nature of filtering preprocess in the existing algorithm is solved by designing a filter that is processed only one time so that fast recognition speed and reduced hardware complexity is obtained. The proposed algorithm is implemented with a FPGA(Field Programmable Gate Array) device and the FAR(False Acceptance Rate) shows five times better than the existing algorithm and the recognition speed is measured to be 100[ms/person].",

author = "Im, {Sang Kyun} and Park, {Hyung Man} and Kim, {Soo Won} and Chung, {Chang Kyung} and Choi, {Hwan Soo}",

year = "2000",

doi = "10.1109/ICCE.2000.854470",

language = "English",

pages = "2--3",

journal = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

issn = "0747-668X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Improved vein pattern extracting algorithm and its implementation

AU - Im, Sang Kyun

AU - Park, Hyung Man

AU - Kim, Soo Won

AU - Chung, Chang Kyung

AU - Choi, Hwan Soo

PY - 2000

Y1 - 2000

N2 - This paper proposes an improved vein pattern extracting algorithm which compensates the loss of vein patterns in the edge area, gives more enhanced and stabilized vein pattern information, and shows better performance than the existing algorithm. Also, the problem arising from the iterative nature of filtering preprocess in the existing algorithm is solved by designing a filter that is processed only one time so that fast recognition speed and reduced hardware complexity is obtained. The proposed algorithm is implemented with a FPGA(Field Programmable Gate Array) device and the FAR(False Acceptance Rate) shows five times better than the existing algorithm and the recognition speed is measured to be 100[ms/person].

AB - This paper proposes an improved vein pattern extracting algorithm which compensates the loss of vein patterns in the edge area, gives more enhanced and stabilized vein pattern information, and shows better performance than the existing algorithm. Also, the problem arising from the iterative nature of filtering preprocess in the existing algorithm is solved by designing a filter that is processed only one time so that fast recognition speed and reduced hardware complexity is obtained. The proposed algorithm is implemented with a FPGA(Field Programmable Gate Array) device and the FAR(False Acceptance Rate) shows five times better than the existing algorithm and the recognition speed is measured to be 100[ms/person].

UR - http://www.scopus.com/inward/record.url?scp=0033702725&partnerID=8YFLogxK

U2 - 10.1109/ICCE.2000.854470

DO - 10.1109/ICCE.2000.854470

M3 - Article

AN - SCOPUS:0033702725

SN - 0747-668X

SP - 2

EP - 3

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

ER -

Improved vein pattern extracting algorithm and its implementation

Abstract

ASJC Scopus subject areas

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