GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. As a result register file consumes a large fraction of the total GPU chip power. This paper explores register file data compression for GPUs to improve power efficiency. Compression reduces the width of the register file read and write operations, which in turn reduces dynamic power. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Compression exploits the value similarity by removing data redundancy of register values. Without decompressing operand values some instructions can be processed inside register file, which enables to further save energy by minimizing data movement and processing in power hungry main execution unit. Evaluation results show that the proposed techniques save 25 percent of the total register file energy consumption and 21 percent of the total execution unit energy consumption with negligible performance impact.
Bibliographical noteFunding Information:
This work was partly supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (NRF-2015R1A2A2A01008281) and Institute for Information &communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. R7117-16-0233, Development of Application Program Optimization Tools for High Performance Computing Systems). This paper is an extension of our previous study, "WarpedCompression: Enabling Power Efficient GPUs through Register Compression," which appeared in the 42nd International Symposium on Computer Architecture.
© 2016 IEEE.
- GPU architectures
- data compression
- register file
ASJC Scopus subject areas
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics