Improving the system-on-a-chip performance for mobile systems by using efficient bus interface

Na Ra Yang, Jeonghwan Lee, Intae Hwang, Cheol Kim Hong, Yoon Gilsang, Sung Woo Chung, Jong Myon Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Minimizing the communication delay is one of the most important design considerations in System-on-a-Chip (SoC) design for mobile systems. In this paper, we present a bus interface design technique, called Efficient Bus Interface (EBI), to reduce the communication delay between the Intellectual Property (IP) core and the memory connected through AMBA3 AXI bus for mobile systems. Several mobile systems require huge multimedia data in the memory to be transferred to the IP core through bus. The proposed EBI is designed to reduce the memory access time by using double buffering, open row access, and bank interleaving. According to our simulations, the proposed EBI improves the performance of the target system by up to 51%.

Original languageEnglish
Title of host publicationProceedings - 2009 WRI International Conference on Communications and Mobile Computing, CMC 2009
Pages606-608
Number of pages3
DOIs
Publication statusPublished - 2009
Event2009 WRI International Conference on Communications and Mobile Computing, CMC 2009 - Kunming, Yunnan, China
Duration: 2009 Jan 62009 Jan 8

Publication series

NameProceedings - 2009 WRI International Conference on Communications and Mobile Computing, CMC 2009
Volume2

Other

Other2009 WRI International Conference on Communications and Mobile Computing, CMC 2009
Country/TerritoryChina
CityKunming, Yunnan
Period09/1/609/1/8

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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