In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100 nm devices. The critical lengths were around 50 nm and 100 nm for NMOS and PMOS devices, respectively.
Bibliographical noteFunding Information:
This work was partly supported by REACHING 22 CATRENE European project, Places2Be ENIAC project and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Global Frontier Research Program, No. 2011-0031638) and the second stage of the Brain Korea 21 Plus Project in 2015. The authors also thank Xavier Mescot and Martine Gri for technical assistance in cryogenic experiment.
© 2015 Published by Elsevier Ltd.
- High-k/metal gate stack
- Neutral defects
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry