In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Ming Shi; Minju Shin; Mireille Mouis; Antoine Cros; Emmanuel Josse; Gyu Tae Kim; Gérard Ghibaudo

doi:10.1016/j.sse.2015.02.012

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Ming Shi, Minju Shin, Mireille Mouis, Antoine Cros, Emmanuel Josse, Gyu Tae Kim, Gérard Ghibaudo

Research output: Contribution to journal › Article › peer-review

18 Citations (Scopus)

Abstract

In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100 nm devices. The critical lengths were around 50 nm and 100 nm for NMOS and PMOS devices, respectively.

Original language	English
Pages (from-to)	13-18
Number of pages	6
Journal	Solid-State Electronics
Volume	112
DOIs	https://doi.org/10.1016/j.sse.2015.02.012
Publication status	Published - 2015

Bibliographical note

Funding Information:
This work was partly supported by REACHING 22 CATRENE European project, Places2Be ENIAC project and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Global Frontier Research Program, No. 2011-0031638) and the second stage of the Brain Korea 21 Plus Project in 2015. The authors also thank Xavier Mescot and Martine Gri for technical assistance in cryogenic experiment.

Publisher Copyright:
© 2015 Published by Elsevier Ltd.

Keywords

FD-SOI
High-k/metal gate stack
Neutral defects
UTBB

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1016/j.sse.2015.02.012

Cite this

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title = "In depth characterization of electron transport in 14 nm FD-SOI CMOS devices",

abstract = "In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100 nm devices. The critical lengths were around 50 nm and 100 nm for NMOS and PMOS devices, respectively.",

keywords = "FD-SOI, High-k/metal gate stack, Neutral defects, UTBB",

author = "Ming Shi and Minju Shin and Mireille Mouis and Antoine Cros and Emmanuel Josse and Kim, {Gyu Tae} and G{\'e}rard Ghibaudo",

note = "Funding Information: This work was partly supported by REACHING 22 CATRENE European project, Places2Be ENIAC project and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Global Frontier Research Program, No. 2011-0031638) and the second stage of the Brain Korea 21 Plus Project in 2015. The authors also thank Xavier Mescot and Martine Gri for technical assistance in cryogenic experiment. Publisher Copyright: {\textcopyright} 2015 Published by Elsevier Ltd.",

year = "2015",

doi = "10.1016/j.sse.2015.02.012",

language = "English",

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AU - Shi, Ming

AU - Shin, Minju

AU - Mouis, Mireille

AU - Cros, Antoine

AU - Josse, Emmanuel

AU - Kim, Gyu Tae

AU - Ghibaudo, Gérard

N1 - Funding Information: This work was partly supported by REACHING 22 CATRENE European project, Places2Be ENIAC project and by the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Global Frontier Research Program, No. 2011-0031638) and the second stage of the Brain Korea 21 Plus Project in 2015. The authors also thank Xavier Mescot and Martine Gri for technical assistance in cryogenic experiment. Publisher Copyright: © 2015 Published by Elsevier Ltd.

PY - 2015

Y1 - 2015

N2 - In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100 nm devices. The critical lengths were around 50 nm and 100 nm for NMOS and PMOS devices, respectively.

AB - In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100 nm devices. The critical lengths were around 50 nm and 100 nm for NMOS and PMOS devices, respectively.

KW - FD-SOI

KW - High-k/metal gate stack

KW - Neutral defects

KW - UTBB

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JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Abstract

Bibliographical note

Keywords

ASJC Scopus subject areas

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