Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories

Hee Dong Kim; Ho Myoung An; Kyoung Chan Kim; Yu Jeong Seo; Tae Geun Kim

doi:10.1088/0268-1242/23/7/075046

Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories

Hee Dong Kim, Ho Myoung An, Kyoung Chan Kim, Yu Jeong Seo, Tae Geun Kim

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 °C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 °C. In addition, the highest traps density of 6.84 × 10¹⁸ cm^-3 was observed with ideal trap distributions for the same sample by capacitance-voltage (C-V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device.

Original language	English
Article number	075046
Journal	Semiconductor Science and Technology
Volume	23
Issue number	7
DOIs	https://doi.org/10.1088/0268-1242/23/7/075046
Publication status	Published - 2008 Jul 1

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1088/0268-1242/23/7/075046

Cite this

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title = "Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories",

abstract = "We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 °C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 °C. In addition, the highest traps density of 6.84 × 1018 cm-3 was observed with ideal trap distributions for the same sample by capacitance-voltage (C-V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device.",

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AU - Kim, Hee Dong

AU - An, Ho Myoung

AU - Kim, Kyoung Chan

AU - Seo, Yu Jeong

AU - Kim, Tae Geun

PY - 2008/7/1

Y1 - 2008/7/1

N2 - We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 °C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 °C. In addition, the highest traps density of 6.84 × 1018 cm-3 was observed with ideal trap distributions for the same sample by capacitance-voltage (C-V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device.

AB - We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 °C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 °C. In addition, the highest traps density of 6.84 × 1018 cm-3 was observed with ideal trap distributions for the same sample by capacitance-voltage (C-V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device.

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Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories

Abstract

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