Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 2

Taeweon Suh; Hsien Hsin S. Lee; Douglas M. Blough

doi:10.1109/MM.2004.50

Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 2

Taeweon Suh, Hsien Hsin S. Lee, Douglas M. Blough

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

The effectiveness of two cache coherence techniques, the snoop-hit buffer and the accompanying region-based cache coherence approach, was evaluated. Two implementations were considered using commercially available embedded processors, the PowerPC 755, a write-back-enhanced Intel 486, and an ARM920T. As the shared-bus protocol, the Advanced System Bus (ASB), an AMBA bus, in the integration of the ARM920T with the PowerPC 755 was considered. The impact of ASB was examined using microbenchmark programs. Overall, results show that ASB provides a viable and effective solution for integrating heterogeneous cache coherence protocols in a system.

Original language	English
Pages (from-to)	70-78
Number of pages	9
Journal	IEEE Micro
Volume	24
Issue number	5
DOIs	https://doi.org/10.1109/MM.2004.50
Publication status	Published - 2004 Sept
Externally published	Yes

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2004.50

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Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 2

Abstract

ASJC Scopus subject areas

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