Integrating cache coherence protocols for heterogeneous multiprocessor systems, Part 2

The effectiveness of two cache coherence techniques, the snoop-hit buffer and the accompanying region-based cache coherence approach, was evaluated. Two implementations were considered using commercially available embedded processors, the PowerPC 755, a write-back-enhanced Intel 486, and an ARM920T. As the shared-bus protocol, the Advanced System Bus (ASB), an AMBA bus, in the integration of the ARM920T with the PowerPC 755 was considered. The impact of ASB was examined using microbenchmark programs. Overall, results show that ASB provides a viable and effective solution for integrating heterogeneous cache coherence protocols in a system.