Integrating networks and memory hierarchies in a multicomputer node architecture

We propose a new multicomputer node architecture, the DI-multicomputer, which can provide higher memory and communication performance than existing multicomputer architectures. By integrating a router onto each processor chip and eliminating the memory bus interface, each processor uses packet routing for both local memory access and internode communication. Multi-packet handling mechanisms are used to implement a high performance memory interface based on packet routing. And the DI-multicomputer network interface directs different types of messages to an appropriate level of the memory hierarchy, providing efficient communication for both short and long messages. Trace-driven simulations show that the communication mechanisms of the DI-multicomputer can achieve up to four times speedup when compared to existing architectures.