Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate: Extraction and compact model

Si/SiO₂ interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO₂ polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution D_it of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.