Investigation of vertically trapped charge locations in Cr-doped-SrTiO 3-based charge trapping memory devices

Yujeong Seo; Min Yeong Song; Ho Myoung An; Yeon Soo Kim; Bae Ho Park; Tae Geun Kim

doi:10.1063/1.4757413

Investigation of vertically trapped charge locations in Cr-doped-SrTiO ₃-based charge trapping memory devices

Yujeong Seo, Min Yeong Song, Ho Myoung An, Yeon Soo Kim, Bae Ho Park, Tae Geun Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO ₃ (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO ₃/Si ₃N ₄ interface to the bulk region of Si ₃N ₄ with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO ₃/Si ₃N ₄ interface by hole injection from the Si substrate into the Si ₃N ₄ layer at a high electric field (E _OX > 7 MV/cm). In addition, some of these charges passing across the SiO ₂ (OX) layer generate many Si-SiO ₂ interface traps (D _it: 1.58 × 10 ¹² cm ^-2 eV ^-1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

Original language	English
Article number	074505
Journal	Journal of Applied Physics
Volume	112
Issue number	7
DOIs	https://doi.org/10.1063/1.4757413
Publication status	Published - 2012 Oct 1

Bibliographical note

Funding Information:
This research was supported by Leading Foreign Research Institute Recruitment Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (No. 2012-00109). The authors also thank for financial support from the Samsung Semiconductor Research Center at Korea University.

ASJC Scopus subject areas

Physics and Astronomy(all)

Access to Document

10.1063/1.4757413

Cite this

@article{945e4ae3e9364a7184bcc61195ee53fb,

title = "Investigation of vertically trapped charge locations in Cr-doped-SrTiO 3-based charge trapping memory devices",

abstract = "In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.",

author = "Yujeong Seo and Song, {Min Yeong} and An, {Ho Myoung} and Kim, {Yeon Soo} and Park, {Bae Ho} and Kim, {Tae Geun}",

note = "Funding Information: This research was supported by Leading Foreign Research Institute Recruitment Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (No. 2012-00109). The authors also thank for financial support from the Samsung Semiconductor Research Center at Korea University.",

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AU - Seo, Yujeong

AU - Song, Min Yeong

AU - An, Ho Myoung

AU - Kim, Yeon Soo

AU - Park, Bae Ho

AU - Kim, Tae Geun

N1 - Funding Information: This research was supported by Leading Foreign Research Institute Recruitment Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (No. 2012-00109). The authors also thank for financial support from the Samsung Semiconductor Research Center at Korea University.

PY - 2012/10/1

Y1 - 2012/10/1

N2 - In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

AB - In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

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