In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO 3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO 3/Si 3N 4 interface to the bulk region of Si 3N 4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO 3/Si 3N 4 interface by hole injection from the Si substrate into the Si 3N 4 layer at a high electric field (E OX > 7 MV/cm). In addition, some of these charges passing across the SiO 2 (OX) layer generate many Si-SiO 2 interface traps (D it: 1.58 × 10 12 cm -2 eV -1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.
Bibliographical noteFunding Information:
This research was supported by Leading Foreign Research Institute Recruitment Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (MEST) (No. 2012-00109). The authors also thank for financial support from the Samsung Semiconductor Research Center at Korea University.
ASJC Scopus subject areas
- Physics and Astronomy(all)