Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors

Byeong Hyeon Lee; Sangsig Kim; Sang Yeol Lee

doi:10.1016/j.sse.2019.03.030

Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors

Byeong Hyeon Lee, Sangsig Kim, Sang Yeol Lee

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

The dependency of the inverter voltage gain on the current level (I _Level ) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode I _Level . To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode I _Level . As the photo stress time increased, the D-mode I _Level increased, and the voltage gains were degraded as a result. This was mainly because the I _Level of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode I _Level , a high voltage gain of 9.85 was obtained at V _DD = 3 V. It is important to note that the S.S value of the E-mode and the I _Level of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors.

Original language	English
Pages (from-to)	5-11
Number of pages	7
Journal	Solid-State Electronics
Volume	156
DOIs	https://doi.org/10.1016/j.sse.2019.03.030
Publication status	Published - 2019 Jun

Bibliographical note

Funding Information:
This work was supported by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20172010104940 ) and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education ( NRF-2017R1D1A3B06033837 ).

Publisher Copyright:
© 2019 Elsevier Ltd

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1016/j.sse.2019.03.030

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title = "Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors",

abstract = " The dependency of the inverter voltage gain on the current level (I Level ) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode I Level . To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode I Level . As the photo stress time increased, the D-mode I Level increased, and the voltage gains were degraded as a result. This was mainly because the I Level of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode I Level , a high voltage gain of 9.85 was obtained at V DD = 3 V. It is important to note that the S.S value of the E-mode and the I Level of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors. ",

author = "Lee, {Byeong Hyeon} and Sangsig Kim and Lee, {Sang Yeol}",

note = "Funding Information: This work was supported by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20172010104940 ) and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education ( NRF-2017R1D1A3B06033837 ). Publisher Copyright: {\textcopyright} 2019 Elsevier Ltd",

year = "2019",

month = jun,

doi = "10.1016/j.sse.2019.03.030",

language = "English",

volume = "156",

pages = "5--11",

journal = "Solid-State Electronics",

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AU - Lee, Byeong Hyeon

AU - Kim, Sangsig

AU - Lee, Sang Yeol

N1 - Funding Information: This work was supported by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20172010104940 ) and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education ( NRF-2017R1D1A3B06033837 ). Publisher Copyright: © 2019 Elsevier Ltd

PY - 2019/6

Y1 - 2019/6

N2 - The dependency of the inverter voltage gain on the current level (I Level ) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode I Level . To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode I Level . As the photo stress time increased, the D-mode I Level increased, and the voltage gains were degraded as a result. This was mainly because the I Level of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode I Level , a high voltage gain of 9.85 was obtained at V DD = 3 V. It is important to note that the S.S value of the E-mode and the I Level of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors.

AB - The dependency of the inverter voltage gain on the current level (I Level ) of depletion mode (D-mode) thin-film transistors (TFTs) has been investigated with only n-type oxide semiconductor-based TFTs. It is clear that the voltage gain strongly depends on the D-mode I Level . To investigate the dependency, photo stress was applied to the D-mode TFT to compare the inverter characteristics depending on the D-mode I Level . As the photo stress time increased, the D-mode I Level increased, and the voltage gains were degraded as a result. This was mainly because the I Level of the D-mode is formed in the high section of the subthreshold slope (S.S) of the enhancement mode (E-mode) TFT when the photo stress was applied. By designing an inverter with a low D-mode I Level , a high voltage gain of 9.85 was obtained at V DD = 3 V. It is important to note that the S.S value of the E-mode and the I Level of the D-mode should be optimized for high voltage gain for the application of next generation integrated circuits and highly sensitive photodetectors.

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Investigation on dependency mechanism of inverter voltage gain on current level of photo stressed depletion mode thin-film transistors

Abstract

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ASJC Scopus subject areas

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