Key Length Reconfigurable ARIA Hardware with S-box Optimization

Junhyun Song; Junghoon Cho; Jongsun Park

doi:10.1109/ICEIC51217.2021.9369812

Key Length Reconfigurable ARIA Hardware with S-box Optimization

Junhyun Song, Junghoon Cho, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16, 822 gate counts. This result showed 23% area reduction compared to previous work.

Original language	English
Title of host publication	2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728191614
DOIs	https://doi.org/10.1109/ICEIC51217.2021.9369812
Publication status	Published - 2021 Jan 31
Event	2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 - Jeju, Korea, Republic of Duration: 2021 Jan 31 → 2021 Feb 3

Publication series

Name	2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Conference

Conference	2021 International Conference on Electronics, Information, and Communication, ICEIC 2021
Country/Territory	Korea, Republic of
City	Jeju
Period	21/1/31 → 21/2/3

Keywords

ARIA
Composite field
Key length reconfigurable
S-box

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Information Systems
Information Systems and Management
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ICEIC51217.2021.9369812

Cite this

Song, J., Cho, J., & Park, J. (2021). Key Length Reconfigurable ARIA Hardware with S-box Optimization. In 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 [9369812] (2021 International Conference on Electronics, Information, and Communication, ICEIC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEIC51217.2021.9369812

Key Length Reconfigurable ARIA Hardware with S-box Optimization. / Song, Junhyun; Cho, Junghoon; Park, Jongsun.
2021 International Conference on Electronics, Information, and Communication, ICEIC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9369812 (2021 International Conference on Electronics, Information, and Communication, ICEIC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Song, J, Cho, J & Park, J 2021, Key Length Reconfigurable ARIA Hardware with S-box Optimization. in 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021., 9369812, 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021, Institute of Electrical and Electronics Engineers Inc., 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021, Jeju, Korea, Republic of, 21/1/31. https://doi.org/10.1109/ICEIC51217.2021.9369812

Song J, Cho J, Park J. Key Length Reconfigurable ARIA Hardware with S-box Optimization. In 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9369812. (2021 International Conference on Electronics, Information, and Communication, ICEIC 2021). doi: 10.1109/ICEIC51217.2021.9369812

@inproceedings{547a1d9ec3334cd4be706739105f7a30,

title = "Key Length Reconfigurable ARIA Hardware with S-box Optimization",

abstract = "As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16, 822 gate counts. This result showed 23% area reduction compared to previous work.",

keywords = "ARIA, Composite field, Key length reconfigurable, S-box",

author = "Junhyun Song and Junghoon Cho and Jongsun Park",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 ; Conference date: 31-01-2021 Through 03-02-2021",

year = "2021",

month = jan,

day = "31",

doi = "10.1109/ICEIC51217.2021.9369812",

language = "English",

series = "2021 International Conference on Electronics, Information, and Communication, ICEIC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 International Conference on Electronics, Information, and Communication, ICEIC 2021",

}

TY - GEN

T1 - Key Length Reconfigurable ARIA Hardware with S-box Optimization

AU - Song, Junhyun

AU - Cho, Junghoon

AU - Park, Jongsun

PY - 2021/1/31

Y1 - 2021/1/31

N2 - As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16, 822 gate counts. This result showed 23% area reduction compared to previous work.

AB - As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16, 822 gate counts. This result showed 23% area reduction compared to previous work.

KW - ARIA

KW - Composite field

KW - Key length reconfigurable

KW - S-box

UR - http://www.scopus.com/inward/record.url?scp=85102967685&partnerID=8YFLogxK

U2 - 10.1109/ICEIC51217.2021.9369812

DO - 10.1109/ICEIC51217.2021.9369812

M3 - Conference contribution

AN - SCOPUS:85102967685

T3 - 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

BT - 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Y2 - 31 January 2021 through 3 February 2021

ER -

Key Length Reconfigurable ARIA Hardware with S-box Optimization

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this