Abstract
As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16, 822 gate counts. This result showed 23% area reduction compared to previous work.
Original language | English |
---|---|
Title of host publication | 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728191614 |
DOIs | |
Publication status | Published - 2021 Jan 31 |
Event | 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 - Jeju, Korea, Republic of Duration: 2021 Jan 31 → 2021 Feb 3 |
Publication series
Name | 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 |
---|
Conference
Conference | 2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 |
---|---|
Country/Territory | Korea, Republic of |
City | Jeju |
Period | 21/1/31 → 21/2/3 |
Bibliographical note
Publisher Copyright:© 2021 IEEE.
Keywords
- ARIA
- Composite field
- Key length reconfigurable
- S-box
ASJC Scopus subject areas
- Artificial Intelligence
- Computer Networks and Communications
- Information Systems
- Information Systems and Management
- Electrical and Electronic Engineering
- Instrumentation