Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

Jang Sik Lee, Jinhan Cho, Chiyoung Lee, Inpyo Kim, Jeongju Park, Yong Mu Kim, Hyunjung Shin, Jaegab Lee, Frank Caruso

Research output: Contribution to journalArticlepeer-review

250 Citations (Scopus)


We describe a versatile approach for preparing flash memory devices composed of polyelectrolyte/gold nanoparticle multilayer films. Anionic gold nanoparticles were used as the charge storage elements, and poly(allylamine)/ poly(styrenesulfonate) multilayers deposited onto hafnium oxide (HfO2)-coated silicon substrates formed the insulating layers. The top contact was formed by depositing HfO2 and platinum. In this study, we investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the 'programmed' and 'erased' states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 × 1012 cm-2 in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.

Original languageEnglish
Pages (from-to)790-795
Number of pages6
JournalNature Nanotechnology
Issue number12
Publication statusPublished - 2007 Dec
Externally publishedYes

ASJC Scopus subject areas

  • Bioengineering
  • Atomic and Molecular Physics, and Optics
  • Biomedical Engineering
  • Materials Science(all)
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


Dive into the research topics of 'Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties'. Together they form a unique fingerprint.

Cite this