This paper presents the design of low-dropout (LDO) regulator optimized on power efficiency and load transient response. As the LDO is always-on block, the quiescent current is a critical parameter of LDO. The proposed circuit includes an op-amp which shows high slew rate with low quiescent current. A voltage damper circuit is included for fast load transient response. A body feedback loop helps the LDO regulator to react to relatively slow distortion of the output voltage. The proposed LDO regulator is fabricated in a 180 nm CMOS process. The test results show that maximum undershoot is 125.9 mV during load transient and 0.177 ns/\mu m figure-of-merit (FOM) at the quiescent current of 0.02532 mA.
|Title of host publication||IEEE International Symposium on Circuits and Systems, ISCAS 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2022|
|Event||2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States|
Duration: 2022 May 27 → 2022 Jun 1
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022|
|Period||22/5/27 → 22/6/1|
Bibliographical noteFunding Information:
This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education under Grant number NRF-2021R1A2C2014652 and NRF-2016R1D1A1B04935233.
© 2022 IEEE.
- body feedback loop
- fast load transient
- LDO regulator
- power efficiency
- quiescent current
- voltage damper
ASJC Scopus subject areas
- Electrical and Electronic Engineering