Abstract
We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs.
Original language | English |
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Pages (from-to) | 219-222 |
Number of pages | 4 |
Journal | Solid-State Electronics |
Volume | 56 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2011 Feb |
Keywords
- Cell transistor
- Gate-controlled diode
- Leakage current
- MOSFET
- RCAT
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry