TY - GEN
T1 - Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation
AU - Park, Hyunchul
AU - Park, Jongsun
N1 - Funding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - Recent SRAM in System-on-Chip (SoC) is required to consume as low power as possible while maintaining its performance and reliability. Lowering supply voltage is an efficient way to reduce power consumption in SRAM. However, SRAM operation becomes highly unstable when its supply voltage is in Near-Threshold Voltage (NTV) region. In this paper, we propose a local bit-line charge-sharing based pre-charging SRAM cell which can sustain performance under NTV region. The proposed cell shows improved read stability in NTV region compared to the previous cells. In addition, by employing transmission gate as access transistors in the proposed cell, better read performance has been achieved at ISO-VMIN condition. The simulation results using 28nm CMOS technology shows that the proposed SRAM cell achieves 2X large read SNM with x1.44-x7.48 speed improvement.
AB - Recent SRAM in System-on-Chip (SoC) is required to consume as low power as possible while maintaining its performance and reliability. Lowering supply voltage is an efficient way to reduce power consumption in SRAM. However, SRAM operation becomes highly unstable when its supply voltage is in Near-Threshold Voltage (NTV) region. In this paper, we propose a local bit-line charge-sharing based pre-charging SRAM cell which can sustain performance under NTV region. The proposed cell shows improved read stability in NTV region compared to the previous cells. In addition, by employing transmission gate as access transistors in the proposed cell, better read performance has been achieved at ISO-VMIN condition. The simulation results using 28nm CMOS technology shows that the proposed SRAM cell achieves 2X large read SNM with x1.44-x7.48 speed improvement.
KW - Local bit-line sharing
KW - Near threshold voltage(NTV)
KW - SRAM
UR - http://www.scopus.com/inward/record.url?scp=85123366193&partnerID=8YFLogxK
U2 - 10.1109/ISOCC53507.2021.9613896
DO - 10.1109/ISOCC53507.2021.9613896
M3 - Conference contribution
AN - SCOPUS:85123366193
T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021
SP - 105
EP - 106
BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International System-on-Chip Design Conference, ISOCC 2021
Y2 - 6 October 2021 through 9 October 2021
ER -