Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation

Hyunchul Park; Jongsun Park

doi:10.1109/ISOCC53507.2021.9613896

Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Recent SRAM in System-on-Chip (SoC) is required to consume as low power as possible while maintaining its performance and reliability. Lowering supply voltage is an efficient way to reduce power consumption in SRAM. However, SRAM operation becomes highly unstable when its supply voltage is in Near-Threshold Voltage (NTV) region. In this paper, we propose a local bit-line charge-sharing based pre-charging SRAM cell which can sustain performance under NTV region. The proposed cell shows improved read stability in NTV region compared to the previous cells. In addition, by employing transmission gate as access transistors in the proposed cell, better read performance has been achieved at ISO-VMIN condition. The simulation results using 28nm CMOS technology shows that the proposed SRAM cell achieves 2X large read SNM with x1.44-x7.48 speed improvement.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	105-106
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613896
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820).

Publisher Copyright:
© 2021 IEEE.

Keywords

Local bit-line sharing
Near threshold voltage(NTV)
SRAM

ASJC Scopus subject areas

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613896

Cite this

Park, H., & Park, J. (2021). Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 105-106). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613896

Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation. / Park, Hyunchul; Park, Jongsun.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 105-106 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, H & Park, J 2021, Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613896

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abstract = "Recent SRAM in System-on-Chip (SoC) is required to consume as low power as possible while maintaining its performance and reliability. Lowering supply voltage is an efficient way to reduce power consumption in SRAM. However, SRAM operation becomes highly unstable when its supply voltage is in Near-Threshold Voltage (NTV) region. In this paper, we propose a local bit-line charge-sharing based pre-charging SRAM cell which can sustain performance under NTV region. The proposed cell shows improved read stability in NTV region compared to the previous cells. In addition, by employing transmission gate as access transistors in the proposed cell, better read performance has been achieved at ISO-VMIN condition. The simulation results using 28nm CMOS technology shows that the proposed SRAM cell achieves 2X large read SNM with x1.44-x7.48 speed improvement.",

keywords = "Local bit-line sharing, Near threshold voltage(NTV), SRAM",

author = "Hyunchul Park and Jongsun Park",

note = "Funding Information: This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820). Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

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Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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