In this study, the logic-in-memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double-gated feedback field-effect transistors. The component transistors reconfigure their operation modes into n- or p-channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on-current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero-bias condition. This study demonstrates that the ternary logic gates are promising candidates for next-generation low-power computing systems.
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF‐2020R1A2C3004538, NRF‐2022M3I7A3046571), the Brain Korea 21 Plus Project of 2022 through the NRF funded by the Ministry of Science, ICT & Future Planning, Samsung Electronics (IO201223‐08257‐01), and the Korea University Grant.
© 2023 The Authors. Advanced Electronic Materials published by Wiley-VCH GmbH.
- field-effect transistor
- multivalued logic
- positive feedback loop
- universal gate
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials