Abstract
Threshold implementation (TI) is a promising coun-termeasure against side-channel attacks (SCA) in the presence of glitches. However, the hardware implementation of TI in S-box needs a large number of D flip-flops to synchronize intermediate signals, which results in a large silicon area and power consump-tion overhead. In this paper, we present the low area and low power TI design technique for advanced encryption standard (AES) S-box. In the proposed approach, instead of using D flip-flops, low-cost synchronization circuits such as customized tri-state XOR gates, tri-state buffers, and D latches are efficiently adopted with critical path replica (CPR) circuits. As a result, the proposed TI S-box implementation with 28nm CMOS process shows up to 33.7% area and 44.3% power savings. The security of the proposed TI AES S-box against side-channel attacks is also verified with test vector leakage assessment (TVLA) tests.
Original language | English |
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Pages (from-to) | 1 |
Number of pages | 1 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
DOIs | |
Publication status | Accepted/In press - 2022 |
Keywords
- Advanced En-cryption Standard (AES)
- Clocks
- D flip-flops
- Delays
- Flip-flops
- glitches
- Latches
- Logic gates
- Power demand
- propagation delay
- S-box
- Synchronization
- synchronization
- Threshold Implementation (TI)
ASJC Scopus subject areas
- Electrical and Electronic Engineering