Low-cost application-aware DVFS for multi-core architecture

Joonho Kong; Jinhang Choi; Lynn Choi; Sung Woo Chung

doi:10.1109/ICCIT.2008.124

Low-cost application-aware DVFS for multi-core architecture

Joonho Kong^*
, Jinhang Choi
, Lynn Choi
, Sung Woo Chung

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

18 Citations (Scopus)

Abstract

As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay² Product (ED² P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED² P, our proposed technique reduces 36.4% and 14.7% of ED ²P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.

Original language	English
Title of host publication	Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
Publisher	IEEE Computer Society
Pages	106-111
Number of pages	6
ISBN (Print)	9780769534077
DOIs	https://doi.org/10.1109/ICCIT.2008.124
Publication status	Published - 2008
Event	3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008 - Busan, Korea, Republic of Duration: 2008 Nov 11 → 2008 Nov 13

Publication series

Name	Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
Volume	2

Other

Other	3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008
Country/Territory	Korea, Republic of
City	Busan
Period	08/11/11 → 08/11/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

ASJC Scopus subject areas

Information Systems
Software

Access to Document

10.1109/ICCIT.2008.124

Cite this

Kong, J., Choi, J., Choi, L., & Chung, S. W. (2008). Low-cost application-aware DVFS for multi-core architecture. In Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008 (pp. 106-111). Article 4682222 (Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008; Vol. 2). IEEE Computer Society. https://doi.org/10.1109/ICCIT.2008.124

Low-cost application-aware DVFS for multi-core architecture. / Kong, Joonho; Choi, Jinhang; Choi, Lynn et al.
Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008. IEEE Computer Society, 2008. p. 106-111 4682222 (Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kong, J, Choi, J, Choi, L & Chung, SW 2008, Low-cost application-aware DVFS for multi-core architecture. in Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008., 4682222, Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008, vol. 2, IEEE Computer Society, pp. 106-111, 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008, Busan, Korea, Republic of, 08/11/11. https://doi.org/10.1109/ICCIT.2008.124

Kong J, Choi J, Choi L , Chung SW. Low-cost application-aware DVFS for multi-core architecture. In Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008. IEEE Computer Society. 2008. p. 106-111. 4682222. (Proceedings - 3rd International Conference on Convergence and Hybrid Information Technology, ICCIT 2008). doi: 10.1109/ICCIT.2008.124

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abstract = "As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2 P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6\% and 54.3\% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2 P, our proposed technique reduces 36.4\% and 14.7\% of ED 2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.",

author = "Joonho Kong and Jinhang Choi and Lynn Choi and Chung, \{Sung Woo\}",

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AU - Choi, Lynn

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N2 - As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2 P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2 P, our proposed technique reduces 36.4% and 14.7% of ED 2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.

AB - As technology scales down, energy/power consumption in the microprocessor has become a serious problem. Especially, as the industry moves on to multi-core processor systems, energy/power management in multi-core systems has become more and more important. In this paper, we propose new DVFS technique in multi-core systems. Our proposed technique finds the optimal DVFS level using Energy-Delay Product (EDP) and Energy-Delay2 Product (ED2 P), which considers energy-efficiency of computation. According to determined DVFS level, the voltage and frequency of processor cores are changed. In our evaluations, our proposed technique shows 5.6% and 54.3% EDP reduction compared to the energy-biased and performance-biased scheme, respectively. In case of ED2 P, our proposed technique reduces 36.4% and 14.7% of ED 2P compared to the energy-biased and performance-biased scheme, respectively. The proposed technique can be a good alternative in future multi-core system where the both energy/power consumption and performance are critical.

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ER -

Low-cost application-aware DVFS for multi-core architecture

Abstract

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UN SDGs

ASJC Scopus subject areas

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