Low cost heterogeneous ARiA S-box implementation for CPA-resistance

Junghoon Cho; Junhyun Song; Jongsun Park

doi:10.1109/ISCAS51556.2021.9401364

Low cost heterogeneous ARiA S-box implementation for CPA-resistance

Junghoon Cho, Junhyun Song, Jongsun Park

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Implementing countermeasure against power analysis-based attack is a critical issue in cryptographic hardware implementation. Protection schemes such as masking or Threshold Implementation (TI) have been proposed for hardware protection, but they have shortages like insufficient protection ability, or excessive hardware overhead. In this paper, we present low cost hetero S-box hardware implementation, where S-box groups for ARIA algorithm can be implemented using the coefficients with different hardware cost. Additional area reduction scheme using isomorphism sharing between S-boxes are also proposed. The proposed heterogeneous ARIS S-box has been implemented using 28nm CMOS process, and it showed 39% area saving with 30% of power saving. The proposed hardware also passed the security test, showing that it is verified as secure against power analysis-based attacks.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401364
Publication status	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 2021 May 22 → 2021 May 28

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	21/5/22 → 21/5/28

Bibliographical note

Funding Information:
This work was supported in part by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591)

Publisher Copyright:
© 2021 IEEE

Keywords

ARIA
Composite field
Correlation power analysis
Hardware sharing

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS51556.2021.9401364

Cite this

Cho, J., Song, J., & Park, J. (2021). Low cost heterogeneous ARiA S-box implementation for CPA-resistance. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401364 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401364

Low cost heterogeneous ARiA S-box implementation for CPA-resistance. / Cho, Junghoon; Song, Junhyun; Park, Jongsun.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401364 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cho, J, Song, J & Park, J 2021, Low cost heterogeneous ARiA S-box implementation for CPA-resistance. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401364, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 21/5/22. https://doi.org/10.1109/ISCAS51556.2021.9401364

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abstract = "Implementing countermeasure against power analysis-based attack is a critical issue in cryptographic hardware implementation. Protection schemes such as masking or Threshold Implementation (TI) have been proposed for hardware protection, but they have shortages like insufficient protection ability, or excessive hardware overhead. In this paper, we present low cost hetero S-box hardware implementation, where S-box groups for ARIA algorithm can be implemented using the coefficients with different hardware cost. Additional area reduction scheme using isomorphism sharing between S-boxes are also proposed. The proposed heterogeneous ARIS S-box has been implemented using 28nm CMOS process, and it showed 39% area saving with 30% of power saving. The proposed hardware also passed the security test, showing that it is verified as secure against power analysis-based attacks.",

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Low cost heterogeneous ARiA S-box implementation for CPA-resistance

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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