Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell

Dongsu Kim; Jongsun Park

doi:10.1109/ISOCC53507.2021.9613950

Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	77-78
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613950
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Funding Information:
This work was supported by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591).

Publisher Copyright:
© 2021 IEEE.

Keywords

lookup-Table
read variation
sot-mram
write energy

ASJC Scopus subject areas

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613950

Cite this

Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell. / Kim, Dongsu; Park, Jongsun.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 77-78 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, D & Park, J 2021, Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 77-78, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613950

@inproceedings{f5a21682d5094fe38add7730971692ed,

title = "Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell",

abstract = "As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.",

keywords = "lookup-Table, read variation, sot-mram, write energy",

author = "Dongsu Kim and Jongsun Park",

note = "Funding Information: This work was supported by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591). Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613950",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "77--78",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

}

TY - GEN

T1 - Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell

AU - Kim, Dongsu

AU - Park, Jongsun

N1 - Funding Information: This work was supported by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591). Publisher Copyright: © 2021 IEEE.

PY - 2021

Y1 - 2021

N2 - As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.

AB - As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.

KW - lookup-Table

KW - read variation

KW - sot-mram

KW - write energy

UR - http://www.scopus.com/inward/record.url?scp=85123384525&partnerID=8YFLogxK

U2 - 10.1109/ISOCC53507.2021.9613950

DO - 10.1109/ISOCC53507.2021.9613950

M3 - Conference contribution

AN - SCOPUS:85123384525

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 77

EP - 78

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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