Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell

Dongsu Kim, Jongsun Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2021, ISOCC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages77-78
Number of pages2
ISBN (Electronic)9781665401746
DOIs
Publication statusPublished - 2021
Event18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of
Duration: 2021 Oct 62021 Oct 9

Publication series

NameProceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference18th International System-on-Chip Design Conference, ISOCC 2021
Country/TerritoryKorea, Republic of
CityJeju Island
Period21/10/621/10/9

Keywords

  • lookup-Table
  • read variation
  • sot-mram
  • write energy

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Information Systems
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell'. Together they form a unique fingerprint.

Cite this