Abstract
As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.
Original language | English |
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Title of host publication | Proceedings - International SoC Design Conference 2021, ISOCC 2021 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 77-78 |
Number of pages | 2 |
ISBN (Electronic) | 9781665401746 |
DOIs | |
Publication status | Published - 2021 |
Event | 18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9 |
Publication series
Name | Proceedings - International SoC Design Conference 2021, ISOCC 2021 |
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Conference
Conference | 18th International System-on-Chip Design Conference, ISOCC 2021 |
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Country/Territory | Korea, Republic of |
City | Jeju Island |
Period | 21/10/6 → 21/10/9 |
Bibliographical note
Funding Information:This work was supported by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591).
Publisher Copyright:
© 2021 IEEE.
Keywords
- lookup-Table
- read variation
- sot-mram
- write energy
ASJC Scopus subject areas
- Computer Networks and Communications
- Information Systems
- Hardware and Architecture
- Electrical and Electronic Engineering