TY - GEN
T1 - Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell
AU - Kim, Dongsu
AU - Park, Jongsun
N1 - Funding Information:
This work was supported by National R&D Program through the National Research Foundation of Korea funded by Ministry of Science and ICT (NRF-2020M3F3A2A01082591).
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.
AB - As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-The-Art SOT-MRAM-based LUT.
KW - lookup-Table
KW - read variation
KW - sot-mram
KW - write energy
UR - http://www.scopus.com/inward/record.url?scp=85123384525&partnerID=8YFLogxK
U2 - 10.1109/ISOCC53507.2021.9613950
DO - 10.1109/ISOCC53507.2021.9613950
M3 - Conference contribution
AN - SCOPUS:85123384525
T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021
SP - 77
EP - 78
BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th International System-on-Chip Design Conference, ISOCC 2021
Y2 - 6 October 2021 through 9 October 2021
ER -