TY - GEN
T1 - Low-power architecture for A 6-bit 1.6GS/s Flash A/D converter
AU - Kim, Jinwoo
AU - Kim, Moo Young
AU - Lee, Ho Kyu
AU - Jung, Inhwa
AU - Kim, Chulwoo
N1 - Copyright:
Copyright 2009 Elsevier B.V., All rights reserved.
PY - 2009
Y1 - 2009
N2 - A 6-bit, 1.6-GS/s, flash ADC with a low-power architecture is presented. The proposed low-power architecture based on an analog input pre-processing method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit, flash ADC. The advantages of the analog input pre-processing method include the low power consumption and small area due to the reduced number of comparators. The proposed flash ADC consumes 240mW at a supply voltage of 1.8V when implemented in a 0.18-μm CMOS technology. The simulated SNDR is 32dB at an input frequency of 200MHz.
AB - A 6-bit, 1.6-GS/s, flash ADC with a low-power architecture is presented. The proposed low-power architecture based on an analog input pre-processing method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit, flash ADC. The advantages of the analog input pre-processing method include the low power consumption and small area due to the reduced number of comparators. The proposed flash ADC consumes 240mW at a supply voltage of 1.8V when implemented in a 0.18-μm CMOS technology. The simulated SNDR is 32dB at an input frequency of 200MHz.
UR - http://www.scopus.com/inward/record.url?scp=70349266457&partnerID=8YFLogxK
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U2 - 10.1109/ICCE.2009.5012232
DO - 10.1109/ICCE.2009.5012232
M3 - Conference contribution
AN - SCOPUS:70349266457
SN - 9781424425594
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
BT - 2009 Digest of Technical Papers International Conference on Consumer Electronics, ICCE 2009
T2 - 2009 International Conference on Consumer Electronics, ICCE 2009
Y2 - 10 January 2009 through 14 January 2009
ER -