Low-power cache with successive tag comparison algorithm

Tae Chan Kim; Chulwoo Kim; Bong Young Chung; Soo Won Kim

doi:10.1007/978-3-540-39762-5_66

Low-power cache with successive tag comparison algorithm

Tae Chan Kim, Chulwoo Kim, Bong Young Chung, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (Central Processor Unit), MCU (Micro Controller Unit), cache, and et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.

Original language	English
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Editors	Jorge Juan Chico, Enrico Macii
Publisher	Springer Verlag
Pages	599-606
Number of pages	8
ISBN (Electronic)	3540200746, 9783540200741
DOIs	https://doi.org/10.1007/978-3-540-39762-5_66
Publication status	Published - 2003

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	2799
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-540-39762-5_66

Cite this

Kim, T. C., Kim, C., Chung, B. Y., & Kim, S. W. (2003). Low-power cache with successive tag comparison algorithm. In J. J. Chico, & E. Macii (Eds.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (pp. 599-606). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2799). Springer Verlag. https://doi.org/10.1007/978-3-540-39762-5_66

Low-power cache with successive tag comparison algorithm. / Kim, Tae Chan; Kim, Chulwoo; Chung, Bong Young et al.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). ed. / Jorge Juan Chico; Enrico Macii. Springer Verlag, 2003. p. 599-606 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2799).

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Kim, TC, Kim, C, Chung, BY & Kim, SW 2003, Low-power cache with successive tag comparison algorithm. in JJ Chico & E Macii (eds), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2799, Springer Verlag, pp. 599-606. https://doi.org/10.1007/978-3-540-39762-5_66

Kim TC, Kim C, Chung BY, Kim SW. Low-power cache with successive tag comparison algorithm. In Chico JJ, Macii E, editors, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag. 2003. p. 599-606. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-39762-5_66

Kim, Tae Chan ; Kim, Chulwoo ; Chung, Bong Young et al. / Low-power cache with successive tag comparison algorithm. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). editor / Jorge Juan Chico ; Enrico Macii. Springer Verlag, 2003. pp. 599-606 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inbook{b0e6b92e0d8b455f80b8587ea2d5970c,

title = "Low-power cache with successive tag comparison algorithm",

abstract = "In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (Central Processor Unit), MCU (Micro Controller Unit), cache, and et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.",

author = "Kim, {Tae Chan} and Chulwoo Kim and Chung, {Bong Young} and Kim, {Soo Won}",

year = "2003",

doi = "10.1007/978-3-540-39762-5_66",

language = "English",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "599--606",

editor = "Chico, {Jorge Juan} and Enrico Macii",

booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

}

TY - CHAP

T1 - Low-power cache with successive tag comparison algorithm

AU - Kim, Tae Chan

AU - Kim, Chulwoo

AU - Chung, Bong Young

AU - Kim, Soo Won

PY - 2003

Y1 - 2003

N2 - In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (Central Processor Unit), MCU (Micro Controller Unit), cache, and et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.

AB - In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (Central Processor Unit), MCU (Micro Controller Unit), cache, and et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.

UR - http://www.scopus.com/inward/record.url?scp=35248823075&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=35248823075&partnerID=8YFLogxK

U2 - 10.1007/978-3-540-39762-5_66

DO - 10.1007/978-3-540-39762-5_66

M3 - Chapter

AN - SCOPUS:35248823075

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 599

EP - 606

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

A2 - Chico, Jorge Juan

A2 - Macii, Enrico

PB - Springer Verlag

ER -

Low-power cache with successive tag comparison algorithm

Abstract

Publication series

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this