Low-power cache with successive tag comparison algorithm

Tae Chan Kim, Chulwoo Kim, Bong Young Chung, Soo Won Kim

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Abstract

    In recent years, power consumption has become one of the most critical design concerns in designing VLSI systems. The reduction of power consumption is inevitably required by the emergence of highly efficient and fast systems, which include CPU (Central Processor Unit), MCU (Micro Controller Unit), cache, and et cetera. This paper introduces a new low-power cache controller with successive tag comparison algorithm. Using these methods, the power consumption of a cache can be reduced. Simulation results show that the power consumption of a cache using the proposed method is reduced by 42% compared with conventional methods.

    Original languageEnglish
    Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    EditorsJorge Juan Chico, Enrico Macii
    PublisherSpringer Verlag
    Pages599-606
    Number of pages8
    ISBN (Electronic)3540200746, 9783540200741
    DOIs
    Publication statusPublished - 2003

    Publication series

    NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
    Volume2799
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349

    ASJC Scopus subject areas

    • Theoretical Computer Science
    • General Computer Science

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