Low power logic design using push-pull pass-transistor logics

Woo Hyun Paik, Hoon Jae Ki, Soo Won Kim

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8µm CMOS process technology. The PPL achieves 36.4ns delay with the power consumption of 18mW/100MHz in the full adder chain and 112MHz speed with 13.4mW/ 50MHz power dissipation in the multiplier.

Original languageEnglish
Pages (from-to)467-478
Number of pages12
JournalInternational Journal of Electronics
Issue number5
Publication statusPublished - 1998 May

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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