Low power logic design using push-pull pass-transistor logics

Woo Hyun Paik; Hoon Jae Ki; Soo Won Kim

doi:10.1080/002072198134571

Low power logic design using push-pull pass-transistor logics

Woo Hyun Paik, Hoon Jae Ki, Soo Won Kim

* Honorary professors

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8µm CMOS process technology. The PPL achieves 36.4ns delay with the power consumption of 18mW/100MHz in the full adder chain and 112MHz speed with 13.4mW/ 50MHz power dissipation in the multiplier.

Original language	English
Pages (from-to)	467-478
Number of pages	12
Journal	International Journal of Electronics
Volume	84
Issue number	5
DOIs	https://doi.org/10.1080/002072198134571
Publication status	Published - 1998 May

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1080/002072198134571

Cite this

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abstract = "This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8µm CMOS process technology. The PPL achieves 36.4ns delay with the power consumption of 18mW/100MHz in the full adder chain and 112MHz speed with 13.4mW/ 50MHz power dissipation in the multiplier.",

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AB - This paper describes a new pass-transistor logic family, named PPL (Push-pull Pass-transistor Logic), for low power which restores outputs by the push-pull operation. Using Push-pull Pass-transistor Logics, 40-stage full adder chain and 8-bit multiplier circuits are designed and fabricated in a 0.8µm CMOS process technology. The PPL achieves 36.4ns delay with the power consumption of 18mW/100MHz in the full adder chain and 112MHz speed with 13.4mW/ 50MHz power dissipation in the multiplier.

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Low power logic design using push-pull pass-transistor logics

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