Low-power pipelined phase accumulator using CMOS-CML hybrid F/Fs for pre-skewing operation

Engineering

• Current Source 100%
• Energy Dissipation 100%
• Reduce Power Consumption 50%
• Operating Speed 50%
• Simulated Result 50%
• Input Data 50%
• Logic Design 50%
• Speed Operation 50%
• Clock Cycle 50%
• Low Power Operation 50%
• Digital Frequency 50%
• Phase Bit 50%

Keyphrases

• Low Power 100%
• Phase Accumulator 100%
• Current Mode Logic 100%
• Current Source 33%
• Energy Consumption Reduction 16%
• On-state Current 16%
• Operating Speed 16%
• Logic Design 16%
• Power Dissipation 16%
• Low Power Operation 16%
• Core Blocks 16%
• Pipelined Architecture 16%
• Low Power Dissipation 16%
• Direct Digital Frequency Synthesizer 16%
• High-speed Operation 16%
• Static CMOS 16%
• Design Topology 16%

Computer Science

• Energy Dissipation 100%
• Reduce Power Consumption 50%
• Operating Speed 50%
• Clock Cycle 50%
• pipelined architecture 50%
• Digital Frequency 50%
• Logic Design 50%