Low-power Programmable Divider for Multi-standard Frequency Synthesizers Using Reset and Modulus Signal Generator

Kyu Young Kim; Woo Kwan Lee; Hoonki Kim; Soo Won Kim

doi:10.1109/ASSCC.2008.4708733

Low-power Programmable Divider for Multi-standard Frequency Synthesizers Using Reset and Modulus Signal Generator

Kyu Young Kim, Woo Kwan Lee, Hoonki Kim, Soo Won Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

This paper proposes a low-power programmable divider for multi-standard frequency synthesizers using a reset and modulus control signal (RMS) generator. The use of RMS generator enables the adaptation of only one counter. This results in less power consumption and effective area. Our design also includes modified D flip-flop design. Proposed divider was designed and fabricated in a standard 0.18-um CMOS technology. Its divide ratio covers from 13 to 1278 at 3GHz. The average power is 3.58μW with 1.5V power supply and effective area is 0.0408mm².

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	77-80
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708733
Publication status	Published - 2008
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 2008 Nov 3 → 2008 Nov 5

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	08/11/3 → 08/11/5

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASSCC.2008.4708733

Cite this

Kim, K. Y., Lee, W. K., Kim, H., & Kim, S. W. (2008). Low-power Programmable Divider for Multi-standard Frequency Synthesizers Using Reset and Modulus Signal Generator. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 77-80). Article 4708733 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008). https://doi.org/10.1109/ASSCC.2008.4708733

Low-power Programmable Divider for Multi-standard Frequency Synthesizers Using Reset and Modulus Signal Generator. / Kim, Kyu Young; Lee, Woo Kwan; Kim, Hoonki et al.
Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. 2008. p. 77-80 4708733 (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, KY, Lee, WK, Kim, H & Kim, SW 2008, Low-power Programmable Divider for Multi-standard Frequency Synthesizers Using Reset and Modulus Signal Generator. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708733, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 77-80, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 08/11/3. https://doi.org/10.1109/ASSCC.2008.4708733

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AB - This paper proposes a low-power programmable divider for multi-standard frequency synthesizers using a reset and modulus control signal (RMS) generator. The use of RMS generator enables the adaptation of only one counter. This results in less power consumption and effective area. Our design also includes modified D flip-flop design. Proposed divider was designed and fabricated in a standard 0.18-um CMOS technology. Its divide ratio covers from 13 to 1278 at 3GHz. The average power is 3.58μW with 1.5V power supply and effective area is 0.0408mm2.

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Low-power Programmable Divider for Multi-standard Frequency Synthesizers Using Reset and Modulus Signal Generator

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