Low-power Skewed Static Logic (S2L) with topology-dependent dual Vt

Chulwoo Kim; Jaesik Lee; Kwang Hyun Baek; Sung Mo Kang

Low-power Skewed Static Logic (S²L) with topology-dependent dual Vt

Chulwoo Kim, Jaesik Lee, Kwang Hyun Baek, Sung Mo Kang

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we describe Skewed Static Logic (S²L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S²L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Noise-tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S²L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S²L with dual Vt reduces delay by 43% and energy×delay by 31% for 1 V power supply over conventional CMOS circuit.

Original language	English
Pages (from-to)	310-314
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication status	Published - 2000
Externally published	Yes
Event	Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: 2000 Sept 13 → 2000 Sept 16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Low-power Skewed Static Logic (S2L) with topology-dependent dual Vt",

abstract = "In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Noise-tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S2L with dual Vt reduces delay by 43% and energy×delay by 31% for 1 V power supply over conventional CMOS circuit.",

author = "Chulwoo Kim and Jaesik Lee and Baek, {Kwang Hyun} and Kang, {Sung Mo}",

year = "2000",

language = "English",

pages = "310--314",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 13th Annual IEEE International ASIC/SOC Conference ; Conference date: 13-09-2000 Through 16-09-2000",

}

TY - JOUR

T1 - Low-power Skewed Static Logic (S2L) with topology-dependent dual Vt

AU - Kim, Chulwoo

AU - Lee, Jaesik

AU - Baek, Kwang Hyun

AU - Kang, Sung Mo

PY - 2000

Y1 - 2000

N2 - In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Noise-tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S2L with dual Vt reduces delay by 43% and energy×delay by 31% for 1 V power supply over conventional CMOS circuit.

AB - In this paper, we describe Skewed Static Logic (S2L) with topology-dependent dual Vt which exhibits low-power, high-performance operation. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Noise-tolerance of proposed technique is presented with simulation results. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S2L reduces energy×delay over MS CMOS by 27-50%. We have also designed 32-bit carry-lookahead adders and verified that S2L with dual Vt reduces delay by 43% and energy×delay by 31% for 1 V power supply over conventional CMOS circuit.

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M3 - Conference article

AN - SCOPUS:0033697267

SN - 1063-0988

SP - 310

EP - 314

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 13th Annual IEEE International ASIC/SOC Conference

Y2 - 13 September 2000 through 16 September 2000

ER -

Low-power Skewed Static Logic (S²L) with topology-dependent dual Vt

Abstract

ASJC Scopus subject areas

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